XR16L2550 Datasheet, PDF (3/45 Pages) Exar Corporation – LOW VOLTAGE DUART WITH 16-BYTE FIFO

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PIN DESCRIPTIONS
Pin Description
NAME
32-QFN
PIN #
44-PLCC
PIN #
DATA BUS INTERFACE
A2
18
29
A1
19
30
A0
20
31
D7
2
9
D6
1
8
D5
32
7
D4
31
6
D3
30
5
D2
29
4
D1
28
3
D0
27
2
IOR#
14
24
IOW#
12
20
CSA#
7
16
CSB#
8
17
INTA
22
33
INTB
21
32
TXRDYA#
-
1
RXRDYA#
-
34
48-TQFP
PIN #
26
27
28
3
2
1
48
47
46
45
44
19
15
10
11
30
29
43
31
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
TYPE
DESCRIPTION
I Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A/B during
a data bus transaction.
IO Data bus lines [7:0] (bidirectional).
I Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
I Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines.
I UART channel A select (active low) to enable UART chan-
nel A in the device for data bus operation.
I UART channel B select (active low) to enable UART chan-
nel B in the device for data bus operation.
O UART channel A Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTA is set to the active mode (active high) and
OP2A# output to a logic 0 when MCR[3] is set to a logic
1. INTA is set to the three state mode and OP2A# to a
logic 1 when MCR[3] is set to a logic 0 (Default).
O UART channel B Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTB is set to the active mode and OP2B# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0 (Default).
O ^{UART channel A Transmitter Ready (active low). The}
output provides the TX FIFO/THR status for transmit
channel A. If it is not used, leave it unconnected.
O UART channel A Receiver Ready (active low). This output
provides the RX FIFO/RHR status for receive channel A.
If it is not used, leave it unconnected.
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