XR-T6165 Datasheet, PDF (9/16 Pages) Exar Corporation – Codirectional Digital Data Processor

XR-T6165
time-slot signals are applied to TS1R (pin 18) and TS2R
(pin 19) and the active time-slot is selected by RTSEL (pin
20). A high level applied to RTSEL selects TS1R and a
low level selects TS2R. Data appearing at PCMOUT is
framed by the read time-slot signal and is guaranteed
glitch free.
Recovery of the 128kHz timing signal is performed by a
variable length counter which is clocked by the 2.048 MHz
signal applied to RXCK2MHz (pin 7). This clock is not
required to be synchronized with any other signals that
are applied to the XR-T6165. However, the RX2MHz
clock (pin 4) may also be used for this function. Positive
input data transitions are used to synchronize this counter
with the data. If synchronization is lost, the counter length
is shortened, and the clock recovery circuit enters a seek
mode until a transition is found.
Octet timing ensures that bit grouping is maintained when
the data is converted from a 64kbps continuous stream to
eight bit 2.048Mbps bursts. Bipolar violations are used to
identify the last bit in each eight bit octet. In the absence of
these violations, for example when receiving a
transmitted alarm condition (transmitter ALARMIN is
high), the circuit will continue to operate in
synchronization with respect to the last received violation.
During this time, the data present at PCMOUT is still
correct as long as synchronization based on the last
received violation is still valid, and the BLS input (pin 3) is
held high. However, if BLS is low and an octet timing
violation is not received, receiver output data is blanked
by forcing PCMOUT to a high level. Also, if eight
successive octet timing violations are not received, the
ALARM output (pin 22) goes to a high level. A high level
applied to the BLANK input (pin 5) will also force
PCMOUT to an all-ones state.
Slip control logic is included in the receiver to
accommodate rate differences between input and output
data. The 64kbps input rate is determined by the remote
transmitter, while the PCMOUT rate is set by RX2MHz
which is a local clock. If this clock is slow, an octet will be
deleted periodically, while the last octet will be repeated
under fast conditions. Octet timing is maintained during
these operations.
APPLICATION INFORMATION
64kbps Codirectional Interface
Figure 6 shows a codirectional interface circuit using the
XR-T6165 with the XR-T6164 line interface. The
XR-T6164 first converts the bipolar 64kbps transmit and
receive signals to active-low TTL compatible data
required by the XR-T6165. The XR-T6165 then performs
the digital functions that are necessary to interface this
64kbps continuous data to a 2.048Mbps PCM time-slot.
The 64kbps signals that have been attenuated and
distorted by the twisted pair cable are
transformer-coupled to the line side of the XR-T6164 as
shown on the left side of Figure 6. A suggested
transformer for both the input and output applications is
the pulse type PE-65535.
The right side of Figure 6 shows the XR-T6164 LOS (Loss
of Signal) output and the XR-T6165 digital inputs and
outputs. All of these pins are TTL compatible. Please
refer to the pin description section of this data sheet for
detailed information about each signal.
Rev. 2.02
9