SP691A Datasheet, PDF (9/24 Pages) Sipex Corporation – Low Power Microprocessor Supervisory with Battery Switch-Over

Pin 12 — CE_OUT — Chip-Enable Output. This
output pin goes LOW only when CE is
IN
LOW and V_CC is above the reset threshold
voltage. If CE_IN is LOW when RESET is
asserted, this output pin will stay low for
16µs or until CE_IN goes HIGH, whichever
occurs first.
Pin 13 — CE_IN — Chip-Enable Input. This is the
input pin to the chip-enable gating circuit.
If this input pin is not used, connect it to
ground or V_OUT.
Pin 14 — WDO — Watchdog Output. If WDI
remains HIGH or LOW longer than the
watchdog timeout period, this output pin
goes LOW and RESET is asserted for the
reset timeout period. This output pin returns
HIGH on the next transition at WDI.
This output pin remains HIGH if WDI is
unconnected.
Pin 15 — RESET — Active LOW Reset Output.
This output pin goes LOW whenever V_CC
falls below the reset threshold. This output
pin will remain low typically for 200ms after
V_CC crosses the reset threshold voltage on
power-up.
Pin 16 — RESET — Active HIGH Reset
Output. This output pin is open drain and
the inverse of RESET.
9
PFI
WDI
OSCSEL
OSCIN
11
Watchdog
Transition
Detector
8
Reset /
7
Watchdog
Timebase
1.25V
Watchdog
Timer
4.65V or
4.40V*
VCC
3
Reset
Generator
CEOUT
Control
VBATT
CEIN
1
13
* 4.65V for the SP691A/800L
4.40V for the SP693A/800M
10
PFO
14
WDO
15
RESET
16
RESET
6
LOWLINE
2
VOUT
5
BATT ON
4 ^GND
12
CEOUT
Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
9