SP691A Datasheet, PDF (18/24 Pages) Sipex Corporation – Low Power Microprocessor Supervisory with Battery Switch-Over

+5V
VCC
PFI
PFO
GND
R1
R2
V-
5.0 - 1.25
R1
=
1.25 - VTRIP
R2
PFO
+5V
0V
V-
*VTRIP ^0V
*VTRIP is a negative voltage
Figure 28. Monitoring a Negative Voltage
Negative-Going V_CC Transients
While asserting resets to the µP during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to short-
duration negative-going VCC transients. It is
usually undesirable to reset the µP when VCC
experiences only small glitches.
Refer to Figure 29 for a graph of the maximum
transient duration vs. the reset-comparator over-
drive for which reset pulses are not generated.
The graph was produced using negative-going
pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated
(reset comparator overdrive). The graph shows
the maximum pulse width a negative-going VCC
transient may typically have without causing a
reset pulse to be issued.
160
0.1µF Capacitor
V_OUT to GND
120
80
Above Line
Reset Generated
40
0
1
10
1000
10000
Reset Comparator Overdrive
(Reset Threshold Voltage - V ), (mV)
CC
Figure 29. Maximum Transient Duration Without
Causing a Reset Pulse vs. Reset Comparator Overdrive
As the amplitude of the transient increases
(i.e., goes farther below the reset threshold), the
maximum allowable pulse width decreases.
Typically, a VCC transient that goes 100mV
below the reset threshold and lasts for 40µs or
less will not cause a reset pulse to be issued.
A 100nF bypass capacitor mounted close to the
VCC pin provides additional transient immunity.
Connecting a Timing Capacitor to OSC_IN
When OSC is connected to ground, OSC
SEL
IN
disconnects from its internal 10µA pull-up and
is internally connected to a +100nA current
source. When a capacitor is connected from
OSC_IN to ground (to select an alternative
watchdog timeout period), the current source
charges and discharges the timing capacitor to
create the oscillator that controls the reset and
watchdog timeout period. To prevent timing
errors, minimize external current leakage
sources at this pin, and locate the capacitor as
close to OSC_IN as possible. The sum of any PC
board leakage plus the OSC capacitor leakage
must be small compared to +100nA.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
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