XRT75VL00D_08 Datasheet, PDF (83/92 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

REV. 1.0.4
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
CHANNEL 1 ADDRESS LOCATION = 0X0E
CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7
BIT 6
Unused
BIT 5
PRBS Enable
Ch_n
BIT 4
RLB_n
BIT 3
LLB_n
BIT 2
E3_n
BIT 1
STS-1/
DS3_n
BIT 0
SR/DR_n
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
• If the LIU has been configured to operate in the Hardware Mode
Then the user should tie the (SR/DR*) pin to "High".
c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing either of the following steps.
• If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA0) to "0" and Bit D0 (JA1) to "1", within the Jitter Attenuator Control
Register, as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
0
0
1
• If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW".
Once the user accomplishes either of these steps, then the Jitter Attenuator (within the LIU) will be configured
to operate with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing either the following steps.
• If the LIU has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
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