XR16M2751 Datasheet, PDF (8/52 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE

XR16M2751
PRELIMINARY
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE
P1.0.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M2751 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs.
Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel
and Motorola mode is shown in Figure 3.
FIGURE 3. XR16M2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW #
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
R/W#
UART_CS#
UART_IRQ#
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART_RESET#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW #
UART
Channel A
CSA#
CSB#
INTA
INTB
UART
Channel B
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
VCC
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
TXB
RXB
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
RIB#
OP2B#
RESET
GND
VCC
Serial Interface of
RS-232, RS-485
(no connect)
Serial Interface of
RS-232, RS-485
(no connect)
Intel Data Bus Interconnections
VCC
VCC
(no connect)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSB#
IOR#
IOW#
CSA#
UART
Channel A
INTA
INTB
UART
Channel B
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
RESET#
VCC
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
TXB
RXB
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
RIB#
OP2B#
GND
Motorola Data Bus Interconnections
2750_int
2.25 to 5.5 Volt VCC
RS-232 Serial Interface
(no connect)
RS-232 Serial Interface
(no connect)
2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 17). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
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