XR-2212 Datasheet, PDF (8/20 Pages) Exar Corporation – Precision Phase-Locked Loop

XR-2212
+1.0
R₀=10K
1MΩ
+0.5
R₀=50K
0
R₀=500K
500K
50K
-0.5
R₀=1MΩ
-1.0
-50 -25
0
V_CC=12V
R₁=12R₀
f₀=1kHz
25
50
75
Temperature (C)
10K
100 125
Figure 9. Typical Center Frequency Drift vs. Temperature
DESCRIPTION OF CIRCUIT CONTROLS
Signal Input (Pin 2): Signal is AC coupled to this terminal.
The internal impedance at Pin 2 is 20kW. Recommended
input signal level is in the range of 10mV to 5V
peak-to-peak.
VCO Current Output (Pin 3): This is a high impedance
(MW) current output terminal which can provide +100mA
drive capability with a voltage swing equal to V_CC. This
output can directly interface with CMOS or NMOS logic
families.
VCO Voltage Output (Pin 5): This terminal provides a
low- impedance ( 50W) buffered output for the VCO. It
can directly interface with low-power Schottley TTL. For
interfacing with standard TTL circuits, a 750W pull-down
resistor from Pin 5 to ground is required. For operation of
the PLL without an external divider, Pin 5 can be DC
coupled to Pin 16.
Op Amp Compensation (Pin 6): The op amp section is
frequency compensated by connecting an external
capacitor from Pin 6 to the amplifier output (Pin 8). For
unity-gain compensation a 20pF capacitor is
recommended.
Op Amp Inputs (Pins 7 and 9): These are the inverting
and the non-inverting inputs for the op amp section. The
common-mode range of the op amp inputs is from +1V to
(V_CC - 1.5) volts.
Op Amp Output (Pin 8): The op amp output is an open-
collector type gain stage and requires a pull-up resistor,
R_L, to V_CC for proper operation. For most applications, the
recommended value of R_L is in 5kW to 10kW range.
Phase Detector Output (Pin 10): This terminal provides
a high-impedance output for the loop phase-detector. The
PLL loop filter is formed by R₁ and C₁ connected to Pin 10
(see Figure 3). With no input signal, or with no
phase-error within the PLL, the DC level at Pin 10 is very
nearly equal to V_REF. The peak voltage swing available at
the phase detector output is equal to $V_REF.
Reference Voltage, V_REF (Pin 11): This pin is internally
biased at the reference voltage level. V_REF:V_REF = V_CC/2
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at Pins 10, 12 and 16. Pin
1 must be bypassed to ground with a 0.1mF capacitor, for
proper operation of the circuit.
VCO Control Input (Pin 12): VCO free-running
frequencies determined by external timing resistor, R₀,
connected from this terminal to ground. For optimum
temperature stability, R₀ must be in the range of 10KW to
100kW (see Figure 9).
VCO Frequency Adjustment: VCO can be fine-tuned
by connecting a potentiometer, R_X, in series with R₀ at Pin
12 (see Figure 11).
This terminal is a low-impedance point, and is internally
biased at a DC level equal to V_REF. The maximum timing
Rev. 2.01
8