XR-2212 Datasheet, PDF (12/20 Pages) Exar Corporation – Precision Phase-Locked Loop

XR-2212
% Deviation of FM
Signal (Df_SM/f₀)
1% or less
1% to 3%
1% to 5%
5% to 10%
10% to 30%
30% to 50%
Recommended Value of
Bandwidth Ratio, N
(N = Df/Df_SM)
10
5
4
3
2
1.5
Table 2.
Recommended values of bandwidth ratio, N, for various
values of FM signal frequency deviation. (Note: N is the
ratio of tracking bandwidth Df to max. signal frequency
deviation, Df_SM).
f) Calculate R_C and R_F to set peak output signal
amplitude. Output signal amplitude, V_OUT, is given
as:
ǒ Ǔ ǒ Ǔǒ Ǔ VOUT +
DfSM
f0
( VREF )
R1
R0
RC ) RF
RC
In most applications, R_F = 100kW is recommended;
then R_C, can be calculated from the above equation
to give desired output swing. The output amplifier can
also be used as a unity-gain voltage follower, by open
circuiting R_C (i.e., R_C = ∞).
Note: All calculated component values except R₀ can be
rounded-off to the nearest standard value, and R₀ can be
varied to fine-tune center frequency, through a series
potentiometer, R_X, (See Figure 11).
Design Example
Demodulator for FM signal with 67kHz carrier frequency
with $5kHz frequency deviation. Supply voltage is +12V
and required peak output swing is $4V.
Step a)
Step b)
f₀ is chosen as 67kHz.
Choose R₀ = 20kW (18kW fixed resistor in
series with 5kW potentiometer).
Step c)
Step d)
Calculate C₀; from design equation (1).
C₀ = 746pF
Calculate R₁. For given FM deviation,
Df_SM/f₀ = 0.0746, and N = 3 from Table 2.
Then:
R₀/R₁ = (3)(0.0746) = 0.224
or:
R₁ = 89.3kW.
Step e): Calculate C1 = (C₀/4) = 186pF.
Step f): Calculate R_C and R_F to get $4V peak
output swing: Let R_F = 100kW. Then,
R_C = 80.6kW.
Note: All values except R₀ can be rounded-off to nearest
standard value.
FREQUENCY SYNTHESIS
Figure 12 shows the generalized circuit connection for
frequency synthesis. In this application an external
frequency divider is connected between the VCO output
(Pin 5) and the phase-detector input (Pin 16). When the
circuit is in lock, the two signals going into the
phase-detector are at the same frequency, or f_S = f₁/N
where N is the modulus of the external frequency divider.
Conversely, the VCO output frequency, f₁ is equal to N_fS.
In the circuit configuration of Figure 12, the external
timing components, R₀ and C₀, set the VCO free running
frequency; R₁ sets the tracking bandwidth and C₁ sets the
loop damping, i.e., the low-pass filter time constant (see
design equations).
The total tracking range of the PLL (see Figure 10),
should be chosen to accommodate the lowest and the
highest frequency, f_max and f_min, to be synthesized. A
recommended choice for most applications is to choose a
tracking half-bandwidth Df, such that:
Df  f_max - f_min
If a variable input frequency and a variable counter
modulus N is used, then the maximum and the minimum
values of output frequency will be:
f_max = N_max (f_S)_max and f_min = N_min (f_S)_min
If a fixed output frequency is desired, i.e. N and f_S are
fixed, then a $10% tracking bandwidth is recommended.
Excessively large tracking bandwidth may cause the PLL
to lock on the harmonics of the input signals; and the small
tracking range increases the “lock-up” or acquisition time.
Design Instructions
For a given performance requirement, the circuit of
Figure 12 can be optimized as follows:
a) Choose center frequency, f₀, to be equal to the output
frequency to be synthesized. If a range of output
Rev. 2.01
12