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SP334CT-L-TR Datasheet, PDF (8/14 Pages) Exar Corporation – Programmable RS-232/RS-485 Transceiver
◁
+5V
0.1µF
0.1µF
9 C1+
12 C1-
11 C2+
13 C2-
5
VCC
SP334
V+ 10
V- 14
0.1µF
0.1µF
0V
25 RS232/RS485
TTL/CMOS
TTL/CMOS
TTL/CMOS
Vcc
400KΩ
27 TI1
T1
Vcc
400KΩ
28 TI2
T2
Vcc
400KΩ
1 TI3
T3
N/C 2
0V
TX1 6
RS-232
TX2 7
RS-232
TX3 4
RS-232
3
N/C
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
19 RX1
20 RX2
21 RX3
22 RX4
23 RX5
R1
RI1 15
5KΩ
R2
RI2 16
5KΩ
R3
RI3 17
5KΩ
R4
RI4 18
5KΩ
R5
RI5 24
5KΩ
RS-232
RS-232
RS-232
RS-232
RS-232
8
GND
26
0V
RXEN
RS-232 MODE
Figure 12. Typical Operating Circuit
0.1µF
0.1µF
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
+5V
9 C1+
12 C1-
11 C2+
13
C2-
5
VCC
SP334
10
V+
14
V-
0.1µF
0.1µF
2 TXEN
Vcc
400KΩ
27 TI1
T1
Vcc
400KΩ
1 TI3
T3
TX2 7
TX1 6
TX4 3
TX3 4
19 RX1
R1
RI1 15
15KΩ
RI2 16
15KΩ
21 RX3
R3
RI4 18
15KΩ
RI3 17
26
15KΩ
RXEN
8 GND
25
RS232/ RS485
RS-485
RS-485
RS-485
RS-485
RS-485
RS-485
RS-485
RS-485
+5V
RS-485 MDDE
Theory of Operation
The SP334 is made up of four separate
circuit blocks — the charge pump, drivers,
receivers, and decoder. Each of these circuit
blocks is described in more detail below.
Charge–Pump
The charge pump is a Exar–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less efficient designs.
The charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 10V
power supplies. Figure 17(a) shows the
waveform found on the positive side of
capacitor C2, and Figure 17(b) shows the
negative side of capacitor C2. There is a
free–running oscillator that controls the four
phases of the voltage shifting. A description
of each phase follows.
Phase 1
— VSS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. C1+ is
then switched to ground and charge on
C1– is transferred to C2–. Since C2+ is con-
nected to +5V, the voltage potential across
capacitor C2 is now 10V.
Phase 2
— VSS transfer — Phase two of the clock con-
nects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal
of C2 to ground, and transfers the generated
–l0V to C3. Simultaneously, the positive side
of capacitor C 1 is switched to +5V and the
negative side is connected to ground.
Phase 3
— VDD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C1 produces
–5V in the negative terminal of C1, which
is applied to the negative side of capacitor
C2. Since C2+ is at +5V, the voltage potential
across C2 is l0V.
Phase 4
— VDD transfer — The fourth phase of the
clock connects the negative terminal of C2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP334_100_090909

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