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| XRT86VL38_07 Datasheet, PDF (72/183 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION | |||
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XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.1
TABLE 45: TRANSMIT Sa AUTO CONTROL REGISTER 2 (TSACR2)
HEX ADDRESS: 0XN132
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 AIS_1_ENB
R/W
0
AIS reception
This bit enables the automatic Sa-bit transmission upon detecting
AIS condition.
Upon detecting the AIS condition, E1 framer will transmit the Alarm
bit (A bit) as â1â, Sa5 bit as â1â, and Sa6 bit as â1â.
See Table 46 for the transmit Sa5, Sa6, and A bit pattern upon
detecting AIS condition.
6 AIS_2_ENB
R/W
0
AIS reception
This bit enables the automatic Sa-bit transmission upon detecting
AIS condition.
Upon detecting the AIS condition, E1 framer will transmit the Alarm
bit (A bit) as â0â, Sa5 bit as â1â, and Sa6 bit as â1â.
See Table 46 for the transmit Sa5, Sa6, and A bit pattern upon
detecting AIS condition.
5 Reserved
-
-
Reserved
4 Reserved
-
-
Reserved
3 CRCREP_ENB[1]
2 CRCREP_ENB[0]
R/W
0
CRC report
These two bits enable the automatic Sa-bit transmission upon
R/W
0
detecting Far End Block Error (i.e. received E bit = 0).
Upon detecting the Far End Block Error (FEBE) condition, E1 framer
will transmit the Alarm bit (A bit) as â0â, Sa5 bit as â1â, Sa6 bit as
â0000â, and E bit as â0â pattern if these two bits are set to â01â.
If these two bits are set to â10â, E1 framer will transmit the Alarm bit
(A bit) as â0â, Sa5 bit as â0â, Sa6 bit as â0000â, and E bit as â0â pattern
upon detecting the Far End Block Error (FEBE).
If these two bits are set to â11â, E1 framer will transmit the Alarm bit
(A bit) as â0â, Sa5 bit as â1â, Sa6 bit as â0001â, and E bit as â1â pattern
upon detecting the Far End Block Error (FEBE).
See Table 46 for the transmit Sa5, Sa6, E, and A bit pattern upon
detecting FEBE condition.
1 CRCDET_ENB
R/W
0
CRC detection
This bit enables the automatic Sa-bit transmission upon detecting
CRC-4 error condition.
Upon detecting CRC-4 error condition, E1 framer will transmit the
Alarm bit (A bit) as â0â, Sa5 bit as â1â, Sa6 bit as â0010â, and E bit as
â1â pattern.
See Table 46 for the transmit Sa5, Sa6, E, and A bit pattern upon
detecting CRC-4 error condition.
0 CRCREC AND
DET_ENB
R/W
0
CRC report and detect
This bit enables automatic Sa-bit transmission upon detecting both
Far End Block Error (FEBE) and CRC-4 error conditions.
Upon detecting both Far End Block Error (FEBE) and CRC-4 error
condition, E1 framer will transmit the Alarm bit (A bit) as â0â, Sa5 bit
as â1â, Sa6 bit as â0011â, and E bit as â1â pattern.
See Table 46 for the transmit Sa5, Sa6, E, and A bit pattern upon
detecting both FEBE and CRC-4 error conditions.
67
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