XRD6414 Datasheet, PDF (7/16 Pages) Exar Corporation – CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter with 4:1 Input Analog Multiplexer

XRD6414
THEORY OF OPERATION
V_IN Analog Input
This part has a switched capacitor type input circuit. The
input impedance changes with the phase of the input
clock. V_IN is sampled at the low to high clock transition
and the digital data changes at the low to high clock
transition. The diagram Figure 4. shows an equivalent
input circuit.
AV_DD
V_IN
AGND
100Ω ^CLK
18pF 100Ω
5pF
CLK
V_RT + V_RB ⁺
1.5pF
C_L
2
−
Figure 4. Equivalent Input Circuit
OFW Overflow (Output)
This signal indicates when the Analog Input (V_IN) goes
above V_RT. The pin is normally at a low logic level. When
V_IN > V_RT, OFW will go high and the data bits (DB0 – DB9)
will show full scale (i.e. all 1s).
OE Output Enable (Input)
This signal controls the 3-state drivers on the digital
outputs DB0 – DB9 and OFW. During normal operation
OE should be held low so that all outputs are enabled.
When OE is driven high DB0 – DB9 and OFW go into high
impedance mode. This control operates asynchronous to
the clock and will only control the output drivers. The
internal output register will get updated if the clock is
running while the outputs are in three-state mode.
OE
DBO-DB9
OFW
0
Enabled
Enabled
1
Three-Stated
Three-Stated
Table 1. Output Enable
Power Supply Sequencing
There are no power supply sequencing issues if DV_DD
and AV_DD of the XRD6414 are driven from the same
supply. Best parametric results, however, are obtained
when DV_DD and AV_DD are driven from separate supplies.
When DV_DD and AV_DD are driven separately, AV_DD must
come up at the same time or before DV_DD, and go down at
the same time or after DV_DD. If the power supply
sequencing in this case is not followed, then damage may
occur to the product due to current flow through the
source-body junction diodes between DV_DD and AV_DD. A
low threshold schottky diode placed locally between
DV_DD and AV_DD can prevent damage to the XRD6414.
Logic Output Interface
The digital output drive circuitry of the XRD6414 was
designed to operate separately from the analog supplies.
The DV_DD pin of the XRD6414 is a separate power supply
dedicated to the logic output drivers. DV_DD is not
connected internally with any of the other power supplies.
Figure 5. illustrates the power supply circuity of the
XRD6414.
DV_DD and DGND connect directly to the digital logic
power of the user’s system isolating the analog and digital
power supplies and grounds. DGND is not common to the
XRD6414 substrate. The XRD6414 substrate is common
only to the packages’ AGND pins. Best spectral
performance is obtained when DV_DD is lowered to 3.3V.
See the power supply sequencing section if AV_DD and
DV_DD are powered separately.
Rev. 1.00
7