SP6652 Datasheet, PDF (7/16 Pages) Sipex Corporation – 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

1 pole rolloff from the error amp pole). The
compensation capacitor becomes:
Cc
=
1
(2π•Rz•pole1)
=
1
(6.28•10kΩ•4kHz)
= 4nF
Soft Start
Soft-start is accomplished by disconnect-
ing the error amp and inserting a constant
2μA current to charge the compensation
capacitor.
When power is first applied and the reference
establishes, the clamp circuit at the COMP
node sets its voltage at one VBE, which is
the bottom of the inductor current range. The
soft-start current continues to charge up the
COMP node, slowly raising the inductor cur-
rent level. The inductor current will increase
at approximately:
(IREFSS / CC)• RPMOS
where:
IREFSS = Soft start constant current
= 2μA nominally
CC = Compensation capacitor
RPMOS = Charging PMOS resistance
For typical circuit values of CC=6.8nF and
RZ=8kΩ, the soft start period is TBD ms.
The inductor current will eventually rise
above the required load current and the out-
put voltage will charge up. During soft-start
the error amp is disconnected and acts as
a comparator. When V(FB) rises above the
reference, the error amp switches to logic
high and ends soft-start, at which point the
error amp output is connected to the capaci-
tated COMP node.
DETAILED DESCRIPTION
The switching frequency will be reduced to
half the normal frequency as long as V(FB)
is below 0.3V, as previously discussed in the
Over Current Protection section.
100% Duty Cycle in Dropout
To extend the battery life in portable applica-
tions, the PWM control logic is set up such
that if the output SR latch has not been reset
by the Current Loop comparator at the end
of a clock cycle, the charge signal continues
to stay high into the beginning of the next
cycle. This will happen naturally when the
converter starts to go into dropout. The slope
compensation ramp is reset every cycle.
External Clock Synchronization
The SP6652 has an internal 1.4MHz clock
that can be defeated by connecting an ex-
ternal clock pulse on the SYNC. The capture
range for clock synchronization is 1.0 to
2.0MHz. When a clock pulse is present on
the SYNC pin, the internal oscillator bias
current is scaled back, handing control of
the clock pulses to the faster external clock.
The pulse width of the clock is approximately
50 ns, whether internally generated or ex-
ternally applied.
Thermal Shutdown
The internal die temperature is monitored by
a comparator that issues a “TOO HOT” sig-
nal when the junction temperature reaches
140˚C, nominally. This signal that inhibits
all internal circuits until the temperature
has decreased to approximately 135˚C, at
which point a normal soft start sequence is
initiated.
Oct10-07 RevJ
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator

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