SP6652 Datasheet, PDF (6/16 Pages) Sipex Corporation – 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

when the output voltage is low. The inductor
current tends to rise until the energy loss
from the discharge resistances are equal to
the energy gained during the charge phase.
For this reason, the clock frequency is cut in
half when the feedback pin is below 0.3V, ef-
fectively reducing the minimum duty cycle in
half. Above V(FB) = 0.3V the clock frequency
is normal (see Typical Operating Character-
istics: Inductor Current vs. V_OUT)
Voltage Loop and Compensation
in PWM Mode
The voltage loop section of the circuit con-
sists of the error amplifier and the translator
circuits (see functional diagram). The input
of the voltage loop is the 0.8V reference volt-
age minus the divided down output voltage
at the feedback pin. The output of the error
amplifier is translated from a ground referred
signal (the COMP node) to a power input
voltage referred signal. The output of the
voltage loop is fed to the positive terminal
of the Current Loop comparator, and repre-
sents the peak inductor current necessary
to close the loop.
DETAILED DESCRIPTION
The total power supply loop is compensated
with a series RC network connected from
the COMP pin to ground. Compensation is
simple due to current-mode control. The
modulator has two dominant poles: one at a
low frequency, and one above the crossover
frequency of the loop, as seen in the graph
below, Linearized Modulator Frequency
Response vs. Inductor Value.
The low frequency pole for L1= 5µH is
4kHz, the second pole is 500kHz, and the
gain-bandwidth is 20kHz. The total loop
crossover frequency is chosen to be 200kHz,
which is 1/6^th of the clock frequency. This
sets the second modulator pole at 2.5 times
the crossover frequency. Therefore the gain
of the error amplifier can be 200kHz/20kHz
= 10 at the first modulator pole of 4kHz. The
error amp transconductance is 1mA/V, so
this sets the RZ resistor value in the com-
pensation network at 10/1mA/V = 10kΩ.
The zero frequency is placed at the first
pole to provide at total system response of
-20dB/decade (the zero from the error amp
cancels the first modulator pole, leaving the
1 ^20K 22.0M 350K
16K 1.6M 40K
12K 1.2M 30K
8K 0.8M 20K
4K 0.4M 10K
>>
0
0
0
2u
3u
4u
5u
6u
7u
8u
9u
10u
1 Mod_pole12 _{Mod_pole2} 3 _{Gbw_modfb}
L1VAL
Conditions: V_IN=5V, V_OUT=3.3V, f_CLK=1.4MHz, C_OUT=10µF, and MC_V=132mV/µs. The inductor is varied from
2µH to 10µH
Linearized Modulator Frequency Response vs. Inductor
Oct10-07 RevJ
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator

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