SP6133 Datasheet, PDF (7/20 Pages) Sipex Corporation – Synchronous Buck Controller

compensation schemes with adequate gain
and phase margins at crossover frequencies
greater than 200 kHz.
The common mode output of the error ampli-
fier (COMP) is 0.9V to 2.2V. Therefore, the
PWM voltage ramp has been set between
1.0V and 2.0V to ensure proper 0% to 100%
duty cycle capability. The voltage loop also
includes two other very important features.
One is a non-synchronous start up mode.
Basically, the GL driver cannot turn on unless
the GH driver has attempted to turn on or
the SS pin has exceeded 1.7V. This feature
prevents the controller from “dragging down”
the output voltage during startup or in fault
modes. The second feature is a 100% duty
cycle timeout that ensures synchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the GH driver is
on for 20 continuous clock cycles, a reset is
given to the PWM flip flop half way through
the 20th cycle. This forces GL to rise for the
remainder of the cycle, in turn refreshing the
BST capacitor.
Gate Drivers
The SP6133 contains a pair of powerful 2Ω
Pull-up and 1.5Ω Pull-down drivers. These
state-of-the-art drivers are designed to drive
an external NFET capable of handling up to
30A. Rise, fall, and non-overlap times have
all been minimized to achieve maximum
efficiency. All drive pins GH, GL, & SWN
are monitored continuously to ensure that
only one external NFET is ever on at any
given time.
Thermal & Short-Circuit Protection
Because the SP6133 is designed to drive
large NFETs running at high current, there is
a chance that either the controller or power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunction-
ing at extreme temperatures.
THEORY OF OPERATION
Over-Current Protection
Over-current is detected by monitoring a
differential voltage across the output induc-
tor as shown in figure 1. Inputs to an over-
current detection comparator, set to trigger
at 60 mV nominal, are connected to the in-
ductor as shown.
Since the average voltage sensed by the
comparator is equal to the product of in-
ductor current and inductor DC resistance
(DCR) then Imax = 60mV / DCR. Solving
this equation for the specific inductor in cir-
cuit 1, Imax = 14.6A. When Imax is reached,
a 220 ms time-out is initiated, during which
top and bottom drivers are turned off. Fol-
lowing the time-out, a restart is attempted.
If the fault condition persists, then the time-
out is repeated (referred to as hiccup).
SP613X
SWN
L = 2.7uH, DCR = 4.mOhm _Vout
RS
RS2
5.K
5.K
ISP
CSP
CS
ISN
6.8nF
0.uF
Figure 1: Over-current detection circuit
Oct 24-06 Rev L
SP6133 Synchronous Buck Controller

© 2006 Sipex Corporation