SP6133 Datasheet, PDF (13/20 Pages) Sipex Corporation – Synchronous Buck Controller

APPLICATION INFORMATION
The power dissipation of the Schottky diode
is determined by:
P_DIODE = 2 • V_F • I_OUT • T_NOL • F_S
where:
T_NOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
Loop Compensation Design
The open loop gain of the whole system can
be divided into the gain of the error ampli-
fier, PWM modulator, buck converter output
stage, and feedback resistor divider. In or-
der to cross over at the selected frequency
fco, the gain of the error amplifier has to
compensate for the attenuation caused by
the rest of the loop at this frequency.
transient response, but often jeopardizes
the system stability. Crossover frequency
should be higher than the ESR zero but
less than 1/5 of the switching frequency.
The ESR zero is contributed by the ESR
associated with the output capacitors and
can be determined by:
ƒ_{z(esr) =}
1
2π • Cout • Resr
The next step is to calculate the complex
conjugate poles contributed by the LC
output filter,
ƒ_P(LC) =
1
√ ^{2π • L • C}out
The goal of loop compensation is to manipu-
late loop frequency response such that its
gain crosses over 0db at a slope of -20db/
dec. The first step of compensation design
is to pick the loop crossover frequency. High
crossover frequency is desirable for fast
When the output capacitors are of a Ceramic
Type, the SP6133 Evaluation Board requires
a Type III compensation circuit to give a phase
boost of 180° in order to counteract the effects
of an under damped resonance of the output
filter at the double pole frequency.
Type III Voltage Loop
Compensation
G_AMP (s) Gain Block
PWM Stage
G_PWM Gain
Block
Output Stage
G_OUT (s) Gain
Block
+ V_REF
(Volts) _{_}
(SRz2Cz2+1)(SR1Cz3+1)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
V_IN
V_{RAMP_PP}
(SR_ESRC_OUT+ 1)
[S²LC_OUT+S(R_ESR+R_DC) C_OUT+1]
V_OUT
(Volts)
Notes: R_ESR = Output Capacitor Equivalent Series Resistance.
R_DC = Output Inductor DC Resistance.
V_{RAMP_PP} = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R_ESR & R_DC
Voltage Feedback
G_FBK Gain Block
R_{2 or} V_REF
V_FBK ^{(R1 + R2) VOUT}
Definitions:
(Volts)
Resr = Output Capacitor Equivalent Series Resistance
Rdc = Output Inductor DC Resistance
Figure 5: SP6133 Voltage
Mode Control Loop with
Loop Dynamic
Vramp _ pp = SP6133 internal RAMP Amplitude Peak to Peak Voltage
Oct 24-06 Rev L
SP6133 Synchronous Buck Controller
13
© 2006 Sipex Corporation