XRT94L31_07 Datasheet, PDF (64/133 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
REV. 1.0.1
PIN # SIGNAL NAME I/O TYPE
DESCRIPTION
AF16
STS1TXA_2_D5
TXHDLCDAT_2_5
TXDS3FP_2
I/O TTL/ Transmit STS-1 Telecom Bus Interface - Channel 2 - Input Data Bus pin
CMOS number 5/Transmit High-Speed HDLC Controller Input Interface block -
Channel 2 - Input Data Bus - Pin 5/Transmit DS3/E3 Frame Boundary
Indicator Output - Channel 2:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-1
Telecom Bus Interface - Input Data Bus pin number 5 - STS1TXA_2_D5:
This input pin along with STS1TXA_2_D[7:6] and STS1TXA_2_D[4:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 2. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_2.
If the STS-1 Telecom Bus Interface (associated with Channel 1) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 2 - Data Bus Input
Pin # 5 - TXHDLCDAT_2_5:
In this configuration, this input pin will function as Bit 5 within the Trans-
mit High-Speed HDLC Controller Input Interface block - Input Data Bus
(e.g., the TxHDLCDat_2[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_2). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_2[7:0] input pins) upon the rising edge of the TxHDLCClk_2
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit DS3/E3
Frame Boundary Indicator Output - Channel 1 - TXDS3FP_2:
This output pin is pulse "High" for one DS3 or E3 clock period, when the
Transmit Payload Data Input Interface block of Channel 2 (within the
XRT94L31) is processing the last bit of a given DS3 or E3 frame.
64