XRT94L31_07 Datasheet, PDF (131/133 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC

XRT94L31
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
1.3.5 INGRESS TIMING FOR STS-1/STM-0 APPLICATIONS............................................................................................ 112
TABLE 13: TIMING INFORMATION FOR THE INGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0 APPLICATIONS(RISING EDGE OF
DS3/E3/STS_1_CLOCK_IN) ..................................................................................................................................... 112
TABLE 14: TIMING INFORMATION FOR THE INGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0 APPLICATIONS(FALLING EDGE OF
DS3/E3/STS_1_CLOCK_IN) ..................................................................................................................................... 112
1.3.6 THE EGRESS DS3/E3/STS-1 INTERFACE TIMING ................................................................................................. 112
FIGURE 17. AN ILLUSTRATION OF THE WAVEFORMS OF THE DS3/E3/STS-1 SIGNALS THAT ARE OUTPUT FROM THE DS3/E3/STS-1 LIU IN-
TERFACE (IN THE RECEIVE/EGRESS DIRECTION) ........................................................................................................... 113
1.3.7 EGRESS TIMING FOR DS3/E3 APPLICATIONS....................................................................................................... 113
TABLE 15: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR DS3/E3 APPLICATIONS(RISING EDGE OF DS3/E3/
STS_1_CLOCK_OUT) .............................................................................................................................................. 113
TABLE 16: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR DS3/E3 APPLICATIONS(FALLING EDGE OF DS3/E3/
STS_1_CLOCK_OUT) .............................................................................................................................................. 113
1.3.8 EGRESS TIMING FOR STS-1/STM-0 APPLICATIONS ............................................................................................. 113
TABLE 17: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0 APPLICATIONSAPPLICATIONS(RISING
EDGE OF DS3/E3/STS_1_CLOCK_OUT) ................................................................................................................... 114
1.3.9 EGRESS TIMING FOR STS-1/STM-0 APPLICATIONS (CONTINUED) .................................................................... 114
TABLE 18: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0 APPLICATIONSAPPLICATIONS(FALL-
ING EDGE OF DS3/E3/STS_1_CLOCK_OUT) ............................................................................................................. 114
1.4 STS-1/STM-0 TELECOM BUS INTERFACE TIMING INFORMATION........................................................... 114
1.4.1 SOME NOTES ABOUT THE STS-1/STM-0 TELECOM BUS INTERFACE ............................................................... 114
1.4.2 THE RECEIVE STS-1/STM-0 TELECOM BUS INTERFACE TIMING........................................................................ 114
FIGURE 18. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE STS-1/STM-0 TELECOM BUS
INTERFACE .................................................................................................................................................................. 115
TABLE 19: TIMING INFORMATION FOR THE RECEIVE STS-1/STM-0 TELECOM BUS INTERFACE ....................................................... 115
1.4.3 THE RECEIVE STS-1/STM-0 TELECOM BUS INTERFACE TIMING (FOR CHANNEL 0 WHEN CONFIGURED TO OP-
ERATE IN THE STS-3/STM-1 MODE)......................................................................................................................... 115
FIGURE 19. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE STS-1/STM-0 TELECOM BUS
INTERFACE (FOR CHANNEL 0) WHEN CONFIGURED TO OPERATE IN THE STS-3/STM-1 MODE......................................... 116
TABLE 20: TIMING INFORMATION FOR THE RECEIVE STS-1/STM-0 TELECOM BUS INTERFACE (WHEN CONFIGURED TO OPERATE IN THE STS-
3/STM-1 MODE) ......................................................................................................................................................... 116
1.4.4 THE TRANSMIT STS-1/STM-0 TELECOM BUS INTERFACE TIMING..................................................................... 116
FIGURE 20. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE INPUT VIA THE TRANSMIT STS-1/STM-0 TELECOM BUS IN-
TERFACE ..................................................................................................................................................................... 117
TABLE 21: TIMING INFORMATION FOR THE TRANSMIT STS-1/STM-0 TELECOM BUS INTERFACE ..................................................... 117
1.4.5 THE TRANSMIT STS-1/STM-0 TELECOM BUS INTERFACE TIMING (FOR CHANNEL 0 WHEN CONFIGURED TO OP-
ERATE IN THE STS-3/STM-1 MODE)......................................................................................................................... 117
FIGURE 21. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE INPUT VIA THE TRANSMIT STS-1/STM-0 TELECOM BUS IN-
TERFACE ASSOCIATED WITH CHANNEL 0 (WHEN CONFIGURED TO OPERATE IN THE STS-3/STM-1 MODE) ....................... 118
TABLE 22: TIMING INFORMATION FOR THE TRANSMIT STS-1/STM-0 TELECOM BUS INTERFACE, FOR CHANNEL 0 WHEN IT HAS BEEN CON-
FIGURED TO OPERATE IN THE STS-3/STM-1 MODE ...................................................................................................... 118
1.5 TRANSMIT TOH OVERHEAD INPUT PORT .................................................................................................. 118
FIGURE 22. ILLUSTRATION OF TIMING WAVE-FORM OF THE TRANSMIT TOH OVERHEAD INPUT PORT.............................................. 119
TABLE 23: TIMING INFORMATION FOR THE TRANSMIT TOH OVERHEAD INPUT PORT ....................................................................... 119
1.6 TRANSMIT POH OVERHEAD INPUT PORT .................................................................................................. 119
FIGURE 23. ILLUSTRATION OF TIMING WAVE-FORM OF THE TRANSMIT POH OVERHEAD INPUT PORT.............................................. 120
TABLE 24: TIMING INFORMATION FOR THE TRANSMIT POH OVERHEAD INPUT PORT ....................................................................... 120
1.7 TRANSMIT ORDERWIRE (E1, F1, E2) BYTE OVERHEAD INPUT PORT .................................................... 120
FIGURE 24. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE TRANSMIT ORDER-WIRE BYTE OVERHEAD INPUT PORT ................. 121
TABLE 25: TIMING INFORMATION FOR THE TRANSMIT ORDER-WIRE BYTE OVERHEAD INPUT PORT ................................................. 121
1.8 TRANSMIT SECTION DCC INSERTION INPUT PORT.................................................................................. 121
FIGURE 25. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE TRANSMIT SECTION DCC OVERHEAD INSERTION PORT.................. 122
TABLE 26: TIMING INFORMATION FOR THE TRANSMIT ORDER-WIRE BYTE OVERHEAD INPUT PORT ................................................. 122
1.9 TRANSMIT LINE DCC INSERTION INPUT PORT.......................................................................................... 122
FIGURE 26. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE TRANSMIT LINE DCC INSERTION INPUT PORT ................................ 123
TABLE 27: TIMING INFORMATION FOR THE TRANSMIT LINE DCC INSERTION INPUT PORT ................................................................ 123
1.10 RECEIVE TOH OVERHEAD OUTPUT PORT ............................................................................................... 123
FIGURE 27. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE TOH OVERHEAD OUTPUT PORT .................................... 124
TABLE 28: TIMING INFORMATION FOR THE RECEIVE TOH OVERHEAD OUTPUT PORT ..................................................................... 124
1.11 RECEIVE POH OVERHEAD OUTPUT PORT............................................................................................... 124
FIGURE 28. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE POH OVERHEAD OUTPUT PORT ..................................... 125
TABLE 29: TIMING INFORMATION FOR THE RECEIVE POH OVERHEAD OUTPUT PORT .................................................................... 125
1.12 RECEIVE ORDERWIRE (E1, F1, E2) BYTES OVERHEAD OUTPUT PORT............................................... 125
FIGURE 29. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE ORDER-WIRE BYTE OVERHEAD OUTPUT PORT................ 126
TABLE 30: TIMING INFORMATION FOR THE RECEIVE ORDER-WIRE BYTE OVERHEAD OUTPUT PORT ............................................... 126
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