XRP7714_1009 Datasheet, PDF (6/29 Pages) Exar Corporation – Quad Channel Digital PWM Step Down Controller

PIN ASSIGNMENT
XRP7714
Quad Channel Digital PWM Step Down Controller
AVDD
1
DVDD
2
GPIO0
3
GPIO1
4
GPIO2
5
GPIO3
6
GPIO4
7
GPIO5
8
ENABLE
9
DGND
10
XRP7714
TQFN
6mm X 6mm
Exposed Pad: AGND
30
GL2
29
LX2
28
GH2
27
BST2
26
VCCD
25
BST4
24
GH4
23
LX4
22
GL4
21
PGND4
Fig. 3: XRP7714 Pin Assignment
PIN DESCRIPTION
Name
VIN1
VIN2
VCCA
VCCD
PGND14
AVDD
DVDD
DGND
AGND
Pin Number
Description
Power source for the internal linear regulators to generate VCCA, VDD and the Standby LDO
39
(LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in UVLO1 fault
generation – if VIN1 falls below the user programmed limit, all channels are shut down. The
VIN1 pin needs to be tied to VIN2 on the board with a short trace.
38
If the Vin2 pin voltage falls below the user programmed UVLO VIN2 level all channels are shut
down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace.
37
Output of the internal 5V LDO. This voltage is internally used to power analog blocks. This pin
should be bypassed with a minimum of 4.7uF to AGND
Gate Drive input voltage. This is not an output voltage. This pin can be connected to VCCA to
26
provide power for the Gate Drive. VCCD should be connected to VCCA with the shortest
possible trace and decouple with a minimum 1µF capacitor. Alternatively, VCCD could be
connected to an external supply (not greater than 5V).
36,31,16,21 Power Ground. Ground connection for the low side gate driver. Connect at low side FET source.
1
Output of the internal 1.8V LDO. This pin should be bypassed with a minimum of 2.2uF to
DGND
2
Input for powering the internal digital logic. This pin should be connected to AVDD.
10
Digital Ground. Connect this pin to the ground plane at the exposed pad with a separate trace.
11
Analog Ground. Connect this pin to the ground plane at the exposed pad with a separate trace
© 2010 Exar Corporation
6/29
Rev. 1.1.4