XRP7714_1009 Datasheet, PDF (14/29 Pages) Exar Corporation – Quad Channel Digital PWM Step Down Controller

XRP7714
Quad Channel Digital PWM Step Down Controller
Another power-up timing concern can be observed with slowly increasing input voltages. If the
UVLO Fault threshold is set to a value higher than the value of VIN when AVDD has stabilized and
the enable is asserted; the UVLO Fault could assert prior to VIN reaching its final value. Increasing
the value of the resistor in the RC delay will slow down the enable signal and prevent a premature
UVLO Fault.
STANDBY LOW DROP-OUT REGULATOR
This 100mA low drop-out regulator can be programmed as 3.3V or 5V in SET_STBLDO_EN_CONFIG
register. Its output is seen on the LDOOUT Pin. This LDO is fully controllable via the Enable Pin
(configured to turn on as soon as power is applied), a GPIO, and/or I²C communication.
The 5V output setting of the regulator is only available if VIN1 is above 6.3V, and the 3.3V output
setting is available for the entire VIN1 range from 4.75 to 25V. The standby LDO should be
bypassed with a minimum of 2.2uF ceramic capacitor.
ENABLING, DISABLING AND RESET
The XRP7714 is enabled via raising the ENABLE Pin high. The chip can then be disabled by
lowering the same ENABLE Pin. There is also the capability for resetting the Chip via an I²C
SOFTRESET Command.
For enabling a specific channel, there are several ways that this can be achieved. The chip can be
configured to enable a channel at start-up as the default configuration residing in the non-volatile
configuration memory of the IC. The channels can also be enabled using GPIO pins and/or an I²C
Bus serial command. The registers that control the channel enable functions are the
SET_EN_CONFIG and SET_CH_EN_I2C.
INTERNAL GATE DRIVERS
The XRP7714 integrates Internal Gate Drivers for all 4 PWM channels. These drivers are optimized
to drive both high-side and low side N-MOSFETs for synchronous operations. Both high side and
low side drivers have the capability of driving 1nF load with 30ns rise and fall time. The drivers
have built-in non-overlapping circuitry to prevent simultaneous conduction of the two MOSFETs.
The built-in non-overlapping feature is disabled when the programmable dead time is selected.
PROGRAMMABLE DEAD TIME
The programmable dead time feature provides customers the flexibility to optimize the system
performance over PWM switching frequency, efficiency and component selections.
There are three registers to control the dead time. The programmable dead time feature is enabled
in the SET_CONTROL_BIT_REG register. If disabled, the built-in dead time control inside the driver
will take over.
The dead time between the turn off of the low side MOSFET and the turn on of high side MOSFET is
controlled by the SET_DT_RISE_CHx. On the other hand, the dead time between the turn off of
high side MOSFET and the turn on of the low side MOSFET is controlled by SET_DT_FALL_CHx. The
actual LSB of the registers is variable depending on the switching frequency.
1
𝑆𝑡𝑒𝑝 𝑆𝑖𝑧𝑒 (𝐿𝑆𝐵) = _{𝑃𝑊𝑀𝑓 × 256}
© 2010 Exar Corporation
14/29
Rev. 1.1.4