XRD98L23 Datasheet, PDF (6/32 Pages) Exar Corporation – 8-Bit, High-speed Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD98L23
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AV =DV =3.3V, ADCCLK=10MHz, 50% Duty Cycle, T =25°C unless otherwise specified.
DD
DD
A
Symbol
Parameter
Min.
System Specifications (MUX + Buffer + PGA + ADC)
SYS_DNL
System DNL
-1.0
SYS_LIN
System Linearity
SYS
System Gain Error
-5.0
GE
IRN
Input Referred Noise
Input Referred Noise
System Timing Specifications
tcklw
ADCCLK Low Pulse Width
tckhw
ADCCLK High Pulse Width
tckpd
ADCCLK Period
100
tsypw
SYNCH Pulse Width
30
trars
Rising ADCCLK to rising
0
SYNCH
tclpw
CLAMP Pulse Width
30
Write Timing Specifications
tsclkw
SCLK Pulse Width
40
tdz
LD Low to SCLK High
20
tds
Input Data Set-up Time
20
tdh
Input Data Hold Time
0
tdl
SCLK High to LD High
50
ADC Digital Output Specifications
tap
Aperture Delay
tdv
Output Data Valid
tsa
SYNCH to ADCCLK (3ch)
20
tsa2
SYNCH to ADCCLK (2ch)
20
tlat
Latency
tlat
Latency
Digital Input Specifications
V
Input High Voltage
AV -1.5
IH
DD
V_IL
Input Low Voltage
I_IH
High Voltage Input Current
I
Low Voltage Input Current
IL
C_IN
Input Capacitance
Typ.
±0.5
±6.0
1.5
0.5
50
50
30
80
8
6
5
5
10
Max.
+2.0
+5.0
Unit
LSB
LSB
%
mV_rms
mV
rms
Conditions
Note 1
No missing codes
Gain=1
Gain=10
ns
ns
ns
ns
SYNCH must rise equal to
or after ADCCLK, See Figure 18
ns Note 2
ns
ns
ns
ns
ns
ns
50
ns
ns 3ch Pixel Md
ns 2ch Pixel Md
cycles Config 00, 11
pixels Config 01, 10
V
0.6
V
µA
µA
pF
Note 1:
Note 2:
System performance is specified for typical digital system timing specifications.
The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
Rev. 1.00
6