XRD9827 Datasheet, PDF (6/32 Pages) Exar Corporation – 12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9827
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AV_DD=DV_DD= 5V, ADCCLK=6MHz, 50% Duty Cycle, T_A=25°C unless otherwise specified.
Symbol
Parameter
Min.
System Specifications (MUX + Buffer + PGA + ADC)
SYS_DNL
System DNL
-1.0
SYS_LIN
System Linearity
SYS_GE
System Gain Error
-5.0
IRN
Input Referred Noise
Input Referred Noise
System Timing Specifications
tcklw
ADCCLK Low Pulse Width 50
tckhw
ADCCLK High Pulse Width 70
tckpd
ADCCLK Period
120
tsypw
SYNCH Pulse Width
30
trars
Rising ADCCLK to rising
0
SYNCH
tclpw
CLAMP Pulse Width
30
Write Timing Specifications
tsclkw
SCLK Pulse Width
40
tdz
LD Low to SCLK High
20
tds
Input Data Set-up Time
20
tdh
Input Data Hold Time
0
tdl
SCLK High to LD High
50
ADC Digital Output Specifications
tap
Aperture Delay
tdv
Output Data Valid
40
tsa
SYNCH to ADCCLK
15
tlat
Latency
tlat
Latency
Digital Input Specifications
V_IH
Input High Voltage
AV_DD-2.5
V
Input Low Voltage
IL
I
High Voltage Input Current
IH
I_IL
Low Voltage Input Current
C
Input Capacitance
IN
Typ.
±0.5
±6.0
1.5
0.5
83
83
166
10
8
6
5
5
10
Max.
+2.3
+5.0
Unit
LSB
LSB
%
mV_rms
mV_rms
Conditions
Note 1
Gain=1
Gain=10
ns
ns
ns
ns
SYNCH must rise equal to
or after ADCCLK, See Figure 18
ns Note 2
ns
ns
ns
ns
ns
ns
ns
ns
cycles
pixels
3ch Pixel Md
Config 00, 11
Config 01, 10
V
1
V
µA
µA
pF
Note 1:
Note 2:
System performance is specified for typical digital system timing specifications.
The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
Rev. 1.20
6