XRD9827 Datasheet, PDF (12/32 Pages) Exar Corporation – 12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9827
CIS
ADCCLK
DB ^[5:0]
[11:6]
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
Pixel N-1
Pixel N
Pixel N+1
tap
tap
tckpd
tckhw tcklw
tdv
tdv
N-8 N-8 N-7 N-7 N-6 N-6 N-5 N-5
MSB LSB MSB LSB MSB LSB MSB LSB
Figure 6. Timing Diagram for Figure 5
ADCCLK
↓
↑
HI
LO
Events
ADC Sample & PGA Start Tracking next Pixel
MSB Data Out
LSB Data Out
ADC Track PGA Output
ADC Hold/Convert
Table 1.
Mode 2. AC Coupled
If the CIS signal has a black reference for the video
signal, an external capacitor C_EXT is used. When
CLAMP (clamp) pin is set high an internal switch allows
one side of the external capacitor to be set to ground.
It then is level shifted to correspond to the bottom ladder
reference voltage of the ADC (Figure 7).
Rev. 1.20
12