XR16V2652 Datasheet, PDF (6/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO

XR16V2652
PRELIMINARY
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
REV. P1.0.0
1.0 PRODUCT DESCRIPTION
The XR16V2652 (V2652) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver
and Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 32-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control, automatic Xon/Xoff and special character software flow control, selectable transmit and receive
FIFO trigger levels, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator
with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps with 4X sampling clock rate. The XR16V2652
is a 2.25 to 3.6V device with 5 volt tolerant inputs. The V2652 is fabricated with an advanced CMOS process.
Enhanced Features
The V2652 DUART provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C2550 or one byte in the ST16C2450. The V2652 is designed to work with low supply
voltage and high performance data communication systems, that require fast data processing time. Increased
performance is realized in the V2652 by the larger transmit and receive FIFOs, FIFO trigger level control and
automatic flow control mechanism. This allows the external processor to handle more networking tasks within
a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms
(This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the
external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 32 byte FIFO in the
V2652, the data buffer will not require unloading/loading for 3.06 ms. This increases the service interval giving
the external CPU additional time for other applications and reducing the overall UART interrupt servicing time.
In addition, the selectable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely
provided for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Rate
The V2652 is capable of operation up to 16 Mbps at 3.3V and 12.5 Mbps at 2.5V with 4X sampling clock rate.
The device can operate with an external 32 MHz crystal at 2.5V on pins XTAL1 and XTAL2, or external clock
source of up to 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the
user can set the prescaler bit for data rates of up to 3.68 Mbps.
The rich feature set of the V2652 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the V2652 is software compatible with previous generation of
UARTs, 16C450, 16C550 and 16C650A.
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