XR20M1170 Datasheet, PDF (59/60 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO

XR20M1170
REV. 1.0.0
I2C/SPI UART WITH 64-BYTE FIFO
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 25
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 26
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 26
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 26
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 27
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 29
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 29
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 30
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 31
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 32
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 32
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6 ............................................................................................................................. 33
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7 ............................................................................................................................. 33
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 34
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 35
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 36
4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) .................... 36
4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ...................................... 36
4.13 TRANSMIT FIFO LEVEL REGISTER (TXLVL) - READ-ONLY ...................................................................... 36
4.14 RECEIVE FIFO LEVEL REGISTER (RXLVL) - READ-ONLY......................................................................... 36
4.15 GPIO DIRECTION REGISTER (IODIR) - READ/WRITE ................................................................................. 37
4.16 GPIO STATE REGISTER (IOSTATE) = READ/WRITE .................................................................................. 37
4.17 GPIO INTERRUPT ENABLE REGISTER (IOINTENA) - READ/WRITE ......................................................... 37
4.18 GPIO CONTROL REGISTER (IOCONTROL) - READ/WRITE ....................................................................... 37
4.19 EXTRA FEATURES CONTROL REGISTER (EFCR) - READ/WRITE............................................................ 37
4.20 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................ 38
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 39
4.21 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 39
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 39
4.21.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 40
TABLE 16: UART RESET STATES .............................................................................................................................................. 41
5.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 42
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 42
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%).............................................. 42
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 42
AC ELECTRICAL CHARACTERISTICS - UART CLOCK .................................................................................... 43
FIGURE 20. CLOCK TIMING............................................................................................................................................................. 43
AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS ........................................................ 44
FIGURE 21. SCL DELAY AFTER RESET .......................................................................................................................................... 45
FIGURE 22. I2C-BUS TIMING DIAGRAM.......................................................................................................................................... 45
FIGURE 23. WRITE TO OUTPUT...................................................................................................................................................... 45
FIGURE 24. MODEM INPUT PIN INTERRUPT ..................................................................................................................................... 46
FIGURE 25. GPIO PIN INTERRUPT.................................................................................................................................................. 46
FIGURE 26. RECEIVE INTERRUPT.................................................................................................................................................... 47
FIGURE 27. RECEIVE INTERRUPT CLEAR......................................................................................................................................... 47
FIGURE 28. TRANSMIT INTERRUPT CLEAR....................................................................................................................................... 47
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS........................................................ 48
FIGURE 29. SPI-BUS TIMING.......................................................................................................................................................... 48
FIGURE 30. SPI WRITE MCR TO DTR OUTPUT SWITCH ................................................................................................................. 49
FIGURE 31. SPI WRITE MCR TO DTR OUTPUT SWITCH ................................................................................................................. 49
FIGURE 32. SPI WRITE THR TO CLEAR TX INT............................................................................................................................. 50
FIGURE 33. READ MSR TO CLEAR MODEM INT ............................................................................................................................. 50
FIGURE 34. READ IOSTATE TO CLEAR GPIO INT .......................................................................................................................... 51
FIGURE 35. READ RHR TO CLEAR RX INT .................................................................................................................................... 51
PACKAGE DIMENSIONS (28 PIN QFN - 5 X 5 X 0.9 mm, 0.50 pitch) ................................ 52
PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 mm, 0.50 pitch) ................................ 53
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