XR16M780 Datasheet, PDF (57/58 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO

XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
GENERAL DESCRIPTION................................................................................................ 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
FIGURE 1. XR16M780 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT FOR 32-PIN QFN AND 48-PIN TQFP PACKAGES IN 16 AND 68 MODE............................................. 2
FIGURE 3. PIN OUT ASSIGNMENT FOR 25-PIN BGA PACKAGE........................................................................................................... 3
ORDERING INFORMATION ............................................................................................................................... 3
PIN DESCRIPTIONS ........................................................................................................ 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8
2.1 CPU INTERFACE ................................................................................................................................................ 8
FIGURE 4. XR16M780 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ............................................................................ 8
2.2 SERIAL INTERFACE........................................................................................................................................... 9
FIGURE 5. XR16M780 TYPICAL SERIAL INTERFACE CONNECTIONS ................................................................................................... 9
FIGURE 6. XR16M780 TYPICAL SERIAL INTERFACE CONNECTIONS ................................................................................................. 10
2.3 DEVICE RESET ................................................................................................................................................. 11
2.4 INTERNAL REGISTERS.................................................................................................................................... 11
2.5 INT OUPUT ........................................................................................................................................................ 11
TABLE 1: INT PIN OPERATION FOR TRANSMITTER ........................................................................................................................... 11
TABLE 2: INT PIN OPERATION FOR RECEIVER ................................................................................................................................ 11
2.6 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 12
FIGURE 7. TYPICAL CRYSTAL CONNECTIONS .................................................................................................................................. 12
2.7 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 13
2.7.1 INDEPENDENT TX/RX BRG......................................................................................................................................... 13
FIGURE 8. BAUD RATE GENERATOR ............................................................................................................................................... 14
TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 14
2.8 TRANSMITTER.................................................................................................................................................. 15
2.8.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 15
2.8.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 15
FIGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 15
2.8.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 16
FIGURE 10. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 16
2.9 RECEIVER ......................................................................................................................................................... 16
2.9.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 16
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 17
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 17
2.10 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 18
2.11 AUTO RTS HYSTERESIS ............................................................................................................................... 18
TABLE 4: AUTO RTS (HARDWARE) FLOW CONTROL ........................................................................................................................ 18
2.12 AUTO CTS FLOW CONTROL......................................................................................................................... 18
FIGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 20
TABLE 5: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 20
2.14 SPECIAL CHARACTER DETECT.................................................................................................................. 20
2.15 NORMAL MULTIDROP MODE........................................................................................................................ 20
2.15.1 AUTO ADDRESS DETECTION .................................................................................................................................. 21
2.16 INFRARED MODE ........................................................................................................................................... 21
FIGURE 14. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 22
2.17 SLEEP MODE WITH AUTO WAKE-UP AND POWER-SAVE FEATURE ...................................................... 22
2.17.1 SLEEP MODE ............................................................................................................................................................. 22
2.17.2 POWER-SAVE FEATURE .......................................................................................................................................... 23
2.17.3 WAKE-UP INTERRUPT .............................................................................................................................................. 23
2.18 INTERNAL LOOPBACK................................................................................................................................. 24
FIGURE 15. INTERNAL LOOPBACK................................................................................................................................................... 24
3.0 UART INTERNAL REGISTERS............................................................................................................. 25
TABLE 6: UART INTERNAL REGISTERS .................................................................................................................................. 25
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 26
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 27
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 27
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 27
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28
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