XRT73L04B Datasheet, PDF(52/64 Page) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73L04B Datasheet, PDF (52/64 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73L04B

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1

COMMAND REGISTER CR4-(n)

X STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n)

b. Operating in the Hardware Mode

To configure Channel (n) to operate in the Analog Lo-

cal Loop-Back Mode, set the LLB_(n) input pin (pin

76, 84, 97 or 105) âHigh" and the RLB_(n) input pin

(pin 77, 85, 96 or 104) "Low".

4.2 THE DIGITAL LOCAL LOOP-BACK MODE.

When a given channel is configured to operate in the

Digital Local Loop-Back Mode, the channel ignores

any signals that are input to the RTIP and RRing in-

put pins. The Transmitting Terminal Equipment trans-

mits clock and data into the XRT73L04B via the TP-

Data, TNData and TxClk input pins. This data is pro-

cessed through the Transmit Clock Duty Cycle Adjust

PLL and the HDB3/B3ZS Encoder block. At this

point, this data is looped back to the HDB3/B3ZS De-

coder block. After this post-Loop-Back data has been

processed through the HDB3/B3ZS Decoder block, it

outputs to the Near-End Receiving Terminal Equip-

ment via the RPOS, RNEG and RxClk output pins.

Figure 34 illustrates the path that the data takes when

the chip is configured to operate in the Digital Local

Loop-Back Mode.

FIGURE 34. THE DIGITAL LOCAL LOOP-BACK PATH WITHIN A GIVEN CHANNEL

RLOL_(n) EXClk_(n)

RTIP_(n)

RRing_(n)

REQEN_(n)

LOSTHR_(n)

SDI

SDO

SClk

CS/(SR/DR)

REGR

TTIP_(n)

TRing_(n)

TxLEV_(n)

TxOFF_(n)

DMO_(n)

AGC/

Equalizer

Slicer

Clock

Recovery

Serial

Processor

Interface

Peak

Detector

LOS Detector

Digital Local

Loop-Back Path

Data

Recovery

Loop MUX

Invert

HDB3/

B3ZS

Decoder

Pulse

Shaping

HDB3/

B3ZS

Encoder

Device

Monitor

Transmit

Logic

Duty Cycle Adjust

Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels

2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in

Hardware Mode.

RxClk_(n)

RPOS_(n)

RNEG_(n)

LCV_(n)

RLOS_(n)

LLB_(n)

RLB_(n)

TAOS_(n)

TPData_(n)

TNData_(n)

TxClk_(n)

MTIP_(n)

MRing_(n)

Configure a channel to operate in the Digital Local

Loop-Back Mode by employing either one of the fol-

lowing two-steps:

a. Operating in the Host Mode

To configure Channel (n) to operate in the Digital Lo-

cal Loop-Back Mode, write a "1" into both the LLB

and RLB bit-fields within Command Register CR4-(n).

COMMAND REGISTER CR4-(n)

X STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n)

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