XRT73L04B Datasheet, PDF(41/64 Page) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73L04B Datasheet, PDF (41/64 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73L04B

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1

When the System Manufacturer is interfacing the Re-

ceive Section of the XRT73L04B to the Cross-Con-

nect, they should be aware of the following facts:

1. All DS3 or STS-1 line signals that are present at

either the DSX-3 or the STSX-1 Cross Connect

are required to meet the Isolated Pulse Template

Requirements per Bellcore GR-499-CORE for

DS3 applications, or Bellcore GR-253-CORE for

STS-1 applications.

2. Bellcore documents state that the amplitude of

these pulses at the DSX-3 or STSX-1 location

can range in amplitude from 360mVpk to

850mVpk.

Bellcore documents stipulate that the Receiving Ter-

minal must be able to receive the pulse template

compliant line signal over a cable length of 0 to 450

feet from the DSX-3 or the STSX-1 Cross-Connect lo-

cation.

These facts are reflected in Figure 23.

Design Considerations for DS3 and STS-1 Appli-

cations

When installing equipment into environments depict-

ed in Figure 23, the system installation personnel

may be able to determine the cable length between

the local terminal equipment and the DSX-3/STSX-1

Cross-Connect Patch-Panel. The cable length be-

tween the local terminal equipment and the DSX-3/

STSX-1 Cross-Connect Patch Panel ranges between

0 and 450 feet.

It is extremely unlikely that the system installation

personnel will know the cable length between the

DSX-3/STSX-1 Cross-Connect Patch-Panel and the

remote terminal equipment. Therefore, we recom-

mend that the Receive Equalizer be enabled by set-

ting the REQEN_(n) input pin or bit-field to â1â.

The only time that the Receive Equalizer should be

disabled is when there is an off-chip equilizer in the

Receive path between the DSX-3/STSX-1 Cross-

Connect and the RTIP_(n)/RRING_(n) input pins, or

in applications where the Receiver is directly monitor-

ing the transmit output signal directly.

3.2.1.2 Design Considerations for E3 Applica-

tions

In E3 System installation, it is recommended that the

Receive Equalizer of the XRT73L04B be enabled by

pulling the REQEN_(n) input pins âHighâ or by setting

the REQEN_(n) bit-fields to â1â.

NOTE: The results of extensive testing indicates that when

the Receive Equalizer is enabled, the XRT73L04B is capa-

ble of receiving an E3 line signal with anywhere from 0 to

12dB of cable loss over the Industrial Temperature range.

â¢ Design Considerations for E3 Applications or if

the Overall Cable Length is known

If during System Installation the overall cable length

is known, then in order to optimize the performance

of the XRT73L04B in terms of receive intrinsic jitter,

etc., enable or disable the Receive Equalizer based

upon the following recommendations:

The Receive Equalizer should be turned ON if the

Receive Section of a given channel is going to re-

ceive a line signal with an overall cable length of 300

feet or greater. Conversely, turn OFF the Receive

Equalizer if the Receive Section of a given channel is

going to receive a line signal over a cable length of

less than 300 feet.

NOTES:

1. If the Receive Equalizer block is turned ON when it

is receiving a line signal over short cable length,

the received line signal may be over-equalized

which could degrade performance by increasing

the amount of jitter that exists in the recovered data

and clock signals or by creating bit-errors

2. The Receive Equalizer has been designed to

counter the frequency-dependent cable loss that a

line signal experiences as it travels from the trans-

mitting terminal to the receiving terminal. However,

the Receive Equalizer was not designed to counter

flat loss where all of the Fourier frequency compo-

nents within the line signal are subject to the same

amount of attenuation. Flat loss is handled by the

AGC block.

Disable the Receive Equalizer block by doing either

of the following.

a. Operating in the Hardware Mode

Setting the REQEN_(n) input pin âLow".

b. Operating in the HOST Mode

Writing a "0" to the REQEN_(n) bit-field within Com-

mand Register CR2, as illustrated below.

COMMAND REGISTER CR-2(n)

Reserved

ALOSDIS_(n)

DLOSDIS_(n)

REQEN_(n)

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