XR16M680 Datasheet, PDF (51/57 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO

REV. 1.0.0
XR16M680
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE]
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
T_SI
ISR is read
TX FIFO fills up
to trigger level
T_WRI
TX FIFO drops
below trigger level
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
TX FIFO
Empty
TXDMA#
51