XR16M752 Datasheet, PDF (50/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
TABLE OF CONTENTS
REV. 1.0.2
GENERAL DESCRIPTION ................................................................................................ 1
APPLICATIONS............................................................................................................................................... 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. XR16M752 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION................................................................................................................................ 3
PIN DESCRIPTIONS ........................................................................................................ 3
1.0 PRODUCT DESCRIPTION....................................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 8
2.1 CPU INTERFACE................................................................................................................................................. 8
FIGURE 3. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS .................................................................................................. 8
2.2 DEVICE RESET ................................................................................................................................................... 9
2.3 CHANNEL A AND B SELECTION....................................................................................................................... 9
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE ............................................................................................................................ 9
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE ............................................................................................................................ 9
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................... 9
2.5 DMA MODE........................................................................................................................................................ 10
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ........................................................................................... 10
2.6 INTA AND INTB OUTPUTS ............................................................................................................................... 10
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 10
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 10
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT .............................................................................. 11
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 11
2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR............................................ 11
FIGURE 5. BAUD RATE GENERATOR ............................................................................................................................................... 12
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 13
2.9 TRANSMITTER .................................................................................................................................................. 13
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ........................................................................................... 14
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 14
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 14
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.10 RECEIVER ....................................................................................................................................................... 15
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 15
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 15
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ......................................................................... 16
2.11 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 16
2.12 AUTO RTS HALT AND RESUME................................................................................................................... 16
2.13 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 16
2.14 AUTO CTS FLOW CONTROL ........................................................................................................................ 17
FIGURE 10. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 17
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 18
2.16 SPECIAL CHARACTER DETECT .................................................................................................................. 18
2.17 INFRARED MODE ........................................................................................................................................... 18
FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 19
2.18 SLEEP MODE WITH AUTO WAKE-UP.......................................................................................................... 19
2.19 INTERNAL LOOPBACK ................................................................................................................................. 20
FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 21
3.0 UART INTERNAL REGISTERS ............................................................................................................. 22
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ....................................................................................... 22
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 25
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 26
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 26
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