XR16M752 Datasheet, PDF (37/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M752/XR68M752
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
4.14.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 8.
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
RESET STATE
DLM, DLL
DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.
They do not reset when the Reset Pin is asserted.
DLD
Bits 7-0 = 0x00
RHR
THR
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x1D
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
TCR
Bits 7-0 = 0x0F
TLR
Bits 7-0 = 0x00
FIFO Rdy
Bits 7-0 = 0x03
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XON2
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XOFF1
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XOFF2
Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
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