XRT73R06 Datasheet, PDF (5/68 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73R06
REV. 1.0.0
Figure 18. Receive Path Block Diagram ......................................................................................................... 30
4.1 RECEIVE LINE INTERFACE ................................................................................................................................ 30
Figure 19. Receive Line InterfaceConnection ................................................................................................ 30
4.2 ADAPTIVE GAIN CONTROL (AGC) .................................................................................................................... 31
4.3 RECEIVE EQUALIZER ........................................................................................................................................ 31
Figure 20. ACG/Equalizer Block Diagram ...................................................................................................... 31
4.3.1 Recommendations for Equalizer Settings ....................................................................................... 31
4.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 31
4.4.1 Data/Clock Recovery Mode ............................................................................................................... 31
4.4.2 Training Mode .................................................................................................................................... 31
4.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 32
4.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 32
4.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 32
TABLE 6: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 32
4.5.3 E3 LOS Condition: ............................................................................................................................. 33
Figure 21. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 33
Figure 22. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 33
4.5.4 Interference Tolerance ...................................................................................................................... 34
Figure 23. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 34
Figure 24. Interference Margin Test Set up for E3. ........................................................................................ 34
TABLE 7: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 35
4.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 36
4.6 B3ZS/HDB3 DECODER ................................................................................................................................... 36
Figure 25. Receiver Data output and code violation timing ............................................................................ 36
5.0 Jitter .................................................................................................................................................. 37
5.1 JITTER TOLERANCE .......................................................................................................................................... 37
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 37
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 37
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 38
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 38
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 38
5.2 JITTER TRANSFER ............................................................................................................................................ 39
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 39
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 39
TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 39
5.2.1 Jitter Generation ................................................................................................................................ 40
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 40
6.0 Diagnostic Features ......................................................................................................................... 41
6.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 41
Figure 30. PRBS MODE ................................................................................................................................. 41
6.2 LOOPBACKS ................................................................................................................................................ 42
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 42
Figure 31. Analog Loopback ........................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 43
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 43
Figure 32. Digital Loopback ............................................................................................................................ 43
Figure 33. Remote Loopback ......................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 44
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 44
7.0 Microprocessor interface Block ..................................................................................................... 46
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... 46
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 46
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 47
TABLE 12: XRT73R06 MICROPROCESSOR INTERFACE SIGNALS ........................................................................ 47
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION ......................................................................................... 48
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ......................................................................................... 49
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