SP6136 Datasheet, PDF (5/18 Pages) Sipex Corporation – Synchronous Buck Controller

PIN DESCRIPTION
PIN PIN
# NAME
DESCRIPTION
1
GL
High current driver output for the low side NFET switch. It is always low if GH is high or
during a fault. Resistor pull down ensures low state at low voltage.
2
PGND
Ground Pin. The power circuitry is referenced to this pin. Return separately from other
ground traces to the (-) terminal of Cout.
3
GND Ground pin. The control circuitry of the IC is referenced to this pin.
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error
Amplifier and serves as the output voltage feedback point for the Buck Converter. The
4
VFB output voltage is sensed and can be adjusted through an external resistor divider.
Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected
and the IC enters hiccup mode.
Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM
5 COMP comparator. An optimal filter combination is chosen and connected to this pin and either
ground or VFB to stabilize the voltage mode loop.
6
EN
Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is
internally pulled to VCC with a 1µA current source.
7
PWRGD
Power Good Output. This open drain output is pulled low when VOUT is outside of the
regulation. Connect an external resistor to pull high.
Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft
8
SS start rate based on the 10µA source current. The SS pin is held low via a 1mA (min) current
during all fault conditions.
9
ISN
Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE
and NSENSE. Offset accuracy +10%.
10
ISP Positive Input for the Inductor Current Sense.
11
SWN
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at
the junction between the two external power MOSFET transistors.
12
GH High current driver output for the high side NFET switch. It is always low if GL is high or during a fault.
13
BST
High side driver supply pin. Connect BST to the external boost diode and capacitor as shown
in the Application Schematic of page 1. High side driver is connected between BST pin and SWN pin.
14
VIN Supply Input -- supplies power to the internal LDO.
15
UVIN
Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground.
Can be overridden with external resistors.
16
VCC
Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an
external 5V supply.
Note: Die attach paddle is internally connected to GND.
General Overview
The SP6136 is a fixed frequency, voltage
mode, synchronous PWM controller opti-
mized for high efficiency. The part has been
designed to be especially attractive for single
supply input voltages ranging between 5V
and 24V.
The heart of the SP6136 is a wide bandwidth
transconductance amplifier designed to ac-
commodate Type II and Type III compensa-
THEORY OF OPERATION
tion schemes. A precision 0.8V reference
present on the positive terminal of the error
amplifier permits the programming of the
output voltage down to 0.8V via the V_FB pin.
The output of the error amplifier, COMP,
compared to a 1V peak-to-peak ramp is
responsible for trailing edge PWM control.
This voltage ramp and PWM control logic
are governed by the internal oscillator that
accurately sets the PWM frequency to 600kHz.
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller

© 2006 Sipex Corporation