SP6136 Datasheet, PDF (10/18 Pages) Sipex Corporation – Synchronous Buck Controller

Lp is due to wiring and PCB traces connecting
input capacitors and switching MOSFETs.
For typical Lp of 12nH and Vin of 12V, di/dt
is 1A/ns. Substituting for di/dt in equation
(6) we get Qgd = 2 nC.
In selecting a package type, the main con-
siderations are cost, power/current handling
capability and space constraints. A larger
package in general offers higher power and
current handling at increased cost. Package
selection can be narrowed down by calculat-
ing the required junction-to-ambient thermal
resistance θja:
{ } θja = Tj(max) - Ta(max)) _{/ P(max)}........... (7)
Where: Tj(max) is the die maximum tem-
perature rating, Ta(max) is maximum ambient
temperature, and P(max) is maximum power
dissipated in the die.
It is common practice to add a guard-band
of 25˚C to the junction temperature rating.
Following this convention, a 150˚C rated
MOSFET will be designed to operate at 125˚C
(i.e., Tj(max) = 125˚C). P(max) = 0.88W (from
section 4) and Ta(max) = 40˚C as specified in
the design example. Substituting in equation
(7) we get θja = 96.6 ˚C/W.
For the top MOSFET, we now have deter-
mined the following requirements; BVdss =
30V, Rds(on) = 10.7mΩ, Qgd = 2 nC and θja
< 96.6˚C/W. An SO-8 MOSFET that meets the
requirements is Vishay-Siliconix’s Si4394DY;
BVdss = 30V, Rds(on) = 9.75mΩ @ Vgs = 4.5V,
Qgd = 2.1nC and θja = 90 ˚C/W.
The bottom MOSFET has the requirements of
BVdss = 30V and Rds(on) = 5.4mΩ. Vishay-
Siliconix’s Si4320DY meets the requirements;
BVdss = 30V, Rds(on) = 4mΩ @ Vgs = 4.5V.
Power Good
Power Good (PWRGD) is an open drain
output that is pulled low when Vout is out-
APPLICATION INFORMATION
side regulation. The PWRGD pin can be
connected to VCC with an external 10KΩ
resistor. During startup, output regulates
when Soft Start (SS) reaches 0.8V (the refer-
ence voltage). PWRGD is enabled when SS
reaches 1.6V. PWRGD output can be used
as a “Power on Reset”. The simplest way to
adjust delay of the “Power on Reset” signal
with respect to Vout in regulation is with the
Soft Start Capacitor (CSS) and is given by:
CSS = (Iss • Tdelay)/0.8 where Iss is the Soft
Start charge current (10µA nominal).
Under Voltage Lock Out (UVLO)
The SP6136 has two separate UVLO com-
parators to monitor the bias (Vcc) and Input
(Vin) voltages independently. The Vcc UVLO
is internally set to 4.25V. The Vin UVLO is
programmable through UVIN pin. When
UVIN pin is greater than 2.5V the SP6136
is permitted to start up pending the removal
of all other faults. A pair of internal resistors
is connected to UVIN as shown in figure 4.
Therefore without external biasing the Vin
start threshold is 9.5V. A small capacitor may
be required between UVIN and GND to filter
out noise. For applications with Vin of 5V or
3.3V, connect UVIN directly to Vin.
SP613X
VI N
R4
40K
U VI N
+
2.5V ON
2.2V OFF ^-
R5
50K
GN D
Figure 4- Internal and external bias of UVIN
To program the Vin start threshold, use a
pair of external resistors as shown. If external
resistors are an order of magnitude smaller
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
10
© 2006 Sipex Corporation