XR16M2550IL32-F Datasheet, PDF (47/47 Pages) Exar Corporation – HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO

XR16M2550
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 25
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 26
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 27
TABLE 12: PARITY SELECTION ........................................................................................................................................................ 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 29
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 30
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 31
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 32
4.11 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 32
TABLE 13: SAMPLING RATE SELECT ............................................................................................................................................... 32
4.12 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 32
4.13 DEVICE REVISION REGISTER (DREV) - READ ONLY................................................................................. 33
4.14 ENHANCED FEATURE REGISTER (EFR) .................................................................................................... 33
TABLE 14: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 33
4.14.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 34
TABLE 15: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 35
5.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 36
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 36
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%).............................................. 36
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 36
AC ELECTRICAL CHARACTERISTICS............................................................................................................. 37
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 38
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 38
FIGURE 15. DATA BUS READ TIMING .............................................................................................................................................. 39
FIGURE 16. DATA BUS WRITE TIMING ............................................................................................................................................ 39
FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 40
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 40
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 41
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 41
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 42
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 42
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm) .................................................................................. 43
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm) ............................................................................... 44
REVISION HISTORY ..................................................................................................................................... 45
TABLE OF CONTENTS ..................................................................................................... I
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