XR16M2750IM48-F Datasheet, PDF (46/53 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M2750
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.0.0
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
Start
Bit
D0:D7
Stop
Bit
IER[1]
enabled
ISR is read
D0:D7
ISR is read
INT*
T_WRI
TXRDY#
T_WRI
T_SRT
T_SRT
T_WRI
D0:D7
ISR is read
T_SRT
T_WT
T_WT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
T_WT
TXNonFIFO
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start
Bit
RX
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
Stop
Bit
INT
T_SSR
RXRDY#
First Byte is
Received in
RX FIFO
T_SSI
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
T_RRI
T_RR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
46