XR16M2750IM48-F Datasheet, PDF (27/53 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.0.0
]
PRIORITY
LEVEL BIT-5
1
0
2
0
3
0
4
0
5
0
6
0
7
1
-
0
XR16M2750
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
0
0
1
1
0 LSR (Receiver Line Status Register)
0
1
1
0
0 RXRDY (Receive Data Time-out)
0
0
1
0
0 RXRDY (Received Data Ready)
0
0
0
1
0 TXRDY (Transmit Ready)
0
0
0
0
0 MSR (Modem Status Register)
1
0
0
0
0 RXRDY (Received Xoff or Special character)
0
0
0
0
0 CTS#, RTS# change of state
0
0
0
0
1 None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR. If it is a special character
interrupt, it can be cleared by reading ISR or it will automatically clear after the next character received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5 FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
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