XRT86VL32_07 Datasheet, PDF (44/174 Pages) Exar Corporation – DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 19: SLIP BUFFER CONTROL REGISTER (SBCR)
REV. V1.2.0
HEX ADDRESS: 0Xn116
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
1-0 SB_ENB[1:0]
R/W
01 Receive Slip Buffer Mode Select
These bits select modes of operation for the receive slip buffer. These two
bits also select the direction of RxSERCLK and RxSYNC in base clock
rate (2.048MHz). The following table shows the corresponding slip buffer
modes as well as the direction of the RxSYNC/RxSERCLK according to
the setting of these two bits.
SB_ENB RECEIVE SLIP BUFFER DIRECTION OF
[1:0]
MODE SELECT
RXSERCLK
DIRECTION OF
RXSYNC
00/11 Receive Slip Buffer is Output
bypassed
Output
01 Slip Buffer Mode
Input
Depends on the
setting of SB_SDIR
(bit 2 of this register)
If SB_SDIR = 0:
RxSYNC = Output
If SB_SDIR = 1:
RxSYNC = Input
10 FIFO Mode.
Input
FIFO data latency
can be programmed
by the 'FIFO Latency
Register' (Address =
0xn117).
Depends on the
setting of SB_SDIR
(bit 2 of this register)
If SB_SDIR = 0:
RxSYNC = Output
If SB_SDIR = 1:
RxSYNC = Input
NOTE:
If the user configures the Receive Slip Buffer to operate in the
“FIFO Mode”, then the user must make sure that the RxSerClk
input pin is synchronized to the Recovered Clock signal for this
particular channel.
TABLE 20: FIFO LATENCY REGISTER (FFOLR)
HEX ADDRESS: 0Xn117
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7-5 Reserved
-
-
Reserved
4-0 Rx Slip Buffer FIFO
Latency[4:0]
R/W 00100 Receive Slip Buffer FIFO Latency[4:0]:
These bits permit the user to specify the “Receive Data” Latency (in
terms of RxSerClk_n clock periods), whenever the Receive Slip
Buffer has been configured to operate in the “FIFO” Mode.
NOTE: These bits are only active if the Receive Slip Buffer has been
configured to operate in the FIFO Mode.
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