XRT73LC00AIV-F Datasheet, PDF (4/61 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE OF CONTENTS
REV. 1.0.2
FEATURES ..................................................................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT73LC00A .......................................................................................................................... 2
ORDERING INFORMATION...............................................................................................2
FIGURE 2. PIN OUT OF THE XRT73LC00A IN THE 44 PIN TQFP ...................................................................................................... 3
PIN DESCRIPTION.............................................................................................................4
ELECTRICAL CHARACTERISTICS ................................................................................12
ABSOLUTE MAXIMUM RATINGS .........................................................................................................12
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................12
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................13
FIGURE 3. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE .................................................................................... 14
FIGURE 4. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE .................................................................................. 14
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR DS3, E3 AND STS-1 RATES................................................................ 14
AC ELECTRICAL CHARACTERISTICS (CONT’D) LINE SIDE PARAMETERS.............................................17
FIGURE 6. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS..................................................................... 18
FIGURE 7. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS ............................................. 18
FIGURE 8. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ............................ 19
FIGURE 9. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE .............................................................................................. 19
AC ELECTRICAL CHARACTERISTICS (CONT.) .....................................................................................20
FIGURE 10. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 20
SYSTEM DESCRIPTION ..................................................................................................21
THE TRANSMIT SECTION...............................................................................................................................21
THE RECEIVE SECTION.................................................................................................................................21
THE MICROPROCESSOR SERIAL INTERFACE ..................................................................................................21
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73LC00A IS OPERATING IN THE HARDWARE MODE .. 22
1.0 SELECTING THE DATA RATE ............................................................................................................23
TABLE 2: SELECTING THE DATA RATE FOR THE XRT73LC00A VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE MODE) ........... 23
COMMAND REGISTER CR4 (ADDRESS = 0X04) .............................................................................................23
TABLE 3: SELECTING THE DATA RATE FOR THE XRT73LC00A VIA THE STS-1/DS3 AND THE E3 BIT-FIELDS WITHIN COMMAND REGISTER
CR4 (HOST MODE) ....................................................................................................................................................... 24
2.0 THE TRANSMIT SECTION ..................................................................................................................24
2.1 THE TRANSMIT LOGIC BLOCK .................................................................................................................... 24
FIGURE 11. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL
EQUIPMENT TO THE TRANSMIT SECTION OF THE XRT73LC00A ....................................................................................... 25
FIGURE 12. HOW THE XRT73LC00A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS .......................................... 25
2.1.1 ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT ............................................................... 25
COMMAND REGISTER CR1 (ADDRESS = 0X01) .............................................................................................26
FIGURE 13. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS ACCEPTING SINGLE-RAIL
DATA FROM THE TERMINAL EQUIPMENT .......................................................................................................................... 26
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY .................................................................... 26
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................................ 26
2.3.1 B3ZS ENCODING ....................................................................................................................................................... 26
FIGURE 14. AN EXAMPLE OF B3ZS ENCODING ............................................................................................................................... 27
2.3.2 HDB3 ENCODING....................................................................................................................................................... 27
FIGURE 15. AN EXAMPLE OF HDB3 ENCODING .............................................................................................................................. 27
2.3.3 ENABLING/DISABLING THE HDB3/B3ZS ENCODER ............................................................................................. 27
COMMAND REGISTER CR2 (ADDRESS = 0X02) .............................................................................................28
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY ............................................................................................ 28
2.4.1 ENABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ......................................................................................... 28
COMMAND REGISTER CR1 (ADDRESS = 0X01) .............................................................................................28
2.4.2 DISABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ........................................................................................ 29
COMMAND REGISTER CR1 (ADDRESS = 0X01) .............................................................................................29
2.4.3 DESIGN GUIDELINE FOR SETTING THE TRANSMIT LINE BUILD-OUT CIRCUIT ................................................ 29
2.4.4 THE TRANSMIT LINE BUILD-OUT CIRCUIT AND E3 APPLICATIONS................................................................... 29
2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE LINE ...................................... 29
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE LINE ................. 30
TRANSFORMER RECOMMENDATIONS ................................................................................................... 30
3.0 THE RECEIVE SECTION .....................................................................................................................32
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