XRT73LC00AIV-F Datasheet, PDF (31/61 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.0.2
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
If the XRT73LC00A is operating in the HOST Mode.
To enable the HDB3/B3ZS Encoder, set the ENDECDIS bit-field in Command Register (CR2) to “0”.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
0
X
X
X
To disable the HDB3/B3ZS Encoder, set the ENDECDIS bit-field in Command Register (CR2) to “1”.
If either of these two methods is employed to disable the HDB3/B3ZS Encoder, the LIU transmits the data onto
the line as it is received via the TPDATA and TNDATA input pins.
2.4 The Transmit Pulse Shaper Circuitry
The Transmit Pulse Shaper Circuitry consists of a Transmit Line Build-Out circuit which can be enabled or
disabled by setting the TXLEV input pin or bit-field to “High” or “Low”. The purpose of the Transmit Line Build-
Out circuit is to permit configuring of the XRT73LC00A to transmit an output pulse which is compliant to either
of the following Bellcore pulse template requirements when measured at the Digital Cross Connect System.
Each of these Bellcore specifications further state that the cable length between the Transmit Output and the
Digital Cross Connect system can range anywhere from 0 to 450 feet.
The Isolated DSX-3 Pulse Template Requirement per Bellcore GR-499-CORE is illustrated in Figure 7.
The Isolated STSX-1 Pulse Template Requirement per Bellcore GR-253-CORE is illustrated in Figure 8.
2.4.1 Enabling the Transmit Line Build-Out Circuit
If the Transmit Line Build-Out Circuit is enabled, the XRT73LC00A outputs shaped pulses onto the line via the
TTIP and TRING output pins.
Do the following to enable the Transmit Line Build-Out circuit in the XRT73LC00A:
 If the XRT73LC00A is operating in the Hardware Mode, set theTXLEV input pin (pin 1) to “Low”
 If the XRT73LC00A is operating in the HOST Mode, set the TXLEV bit-field to “0” as illustrated below.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
TXOFF TAOS
0
X
D2
TXCLKINV
X
D1
TXLEV
0
D0
TXBIN
X
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