XRK32510 Datasheet, PDF (4/7 Pages) Exar Corporation – 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS

XRK32510
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
xr
REV. 1.0.1
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage (AVDD)
Supply Voltage (VDD)
Logic Inputs
Ambient Operating Temperature Range
Storage Temperature Range
AVDD < (VDD +0.7V)
4.3V
GND- 0.5V to VDD + 0.5V
0°C to +70°C
-65°C to +150°C
ELECTRICAL CHARACTERISTICS -OUTPUT
T_A = 0 - 70°C, VDD = AVDD = 3.3V +/- 10%, C_L = 20 - 30pF, R_L = 470Ω, (unless otherwise stated)
SYMBOL
PARAMETER
MIN
TYP
MAX UNITS
CONDITIONS
R_DSP
Output Impedance
36
Ω
V_O = VDD/2
R_DSN
Output Impedance
32
Ω
V_O = VDD/2
V_OH Output High Voltage 2.4
3.0
V
I_OH = -8mA
V_OL
Output Low Voltage
0.2
I_OL = 8mA
I_OH
Output High Current
-33
-13.6
mA
-48
-22
V_OH = 2.4V
V_OH = 2.0V
19
28
I_OL
Output Low Current
13
19
mA
V_OL = 0.8V
V_OL =0.55V
T_r
Rise Time¹
0.5
0.8
2.1
ns
V_OH = 2.0V, V_OL = 0.8V
T_f
Fall Time¹
0.5
0.9
2.7
ns
V_OL = 0.8V, V_OH = 2.0V
D_t
Duty Cycle¹
45
50
55
%
VT = 1.5V, C_L = 30pF
Tcyc-cyc _{Cycle to Cycle Jitter}¹
28.7
100
25
75
ps
@66 - 100MHz, loaded outputs
@133MHz, loaded outputs
T_jABS
Absolute Jitter¹
57
ps
10,000 cycles, C_L = 30 pF
T_sk
Skew¹
29
150
ps
VT = 1.5V (Window) Output to Output
T_pe
Phase Error¹
-150
150
ps
V_T = VDD/2, CLK_IN to FB_IN
T_pej
Phase Error Jitter¹
-50
35
50
ps V_T = VDD/2, CLK_IN to FB_IN, Delay Jitter
D_R1
Delay Input to
Output¹
3.5
3.7
ns
V_T = 1.5V, PLL Disabled (AVDD = 0)
NOTE:
1. Guaranteed by design, not 100% tested in production
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