XRK32510 Datasheet, PDF (3/7 Pages) Exar Corporation – 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS

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REV. 1.0.1
XRK32510
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
PIN DESCRIPTIONS
PIN #
PIN NAME
1
AGND
2
VDD
10
VDD
14
VDD
11
OE
12
FB_OUT
13
FB_IN
3
QA0
4
QA1
5
QA2
8
QA3
9
QA4
15
QA5
16
QA6
17
QA7
20
QA8
21
QA9
22
VDD
23
AVDD
24
CLK_IN
TYPE
****
****
Analog Ground
3.3V Power Supply
PIN DESCRIPTION
INPUT
OUTPUT
INPUT
OUTPUT(S)
Output Enable:
"High" = Normal operation, Clock outputs (QA[0:9]) enabled
"Low" = Clock outputs (QA[0:9]) disabled
Feedback Output:
When this pin is connected to FB_IN, the propagation delay from
CLK_IN to any of the 10 QA pins will be nearly zero.
Feedback Input
Buffered Clock Outputs:
These 10 outputs provide low-skew, low jitter, 50% duty cycle renditions
of CLK_IN
****
****
INPUT
3.3V Digital Power Supply
3.3V Analog Supply:
If this pin is connected to ground, the PLL is disabled and will be
bypassed and the CLK_IN signal will be connected directly to the output
buffers of the 10 QA pins.
Reference Clock Input
FUNCTIONAL OPERATION
INPUTS
OE
AVDD
0
3.3V
1
3.3V
0
0
1
0
OUTPUTS
QA[0:9]
FB_OUT
0
Driven
Driven
Driven
BUFFER MODE
0
Driven
Driven
Driven
SOURCE
PLL
PLL
PLL
CONDITION
ON
ON
CLK_IN
CLK_IN
OFF
OFF
3