DAN-130 Datasheet, PDF (4/11 Pages) Exar Corporation – EXAR’S DUARTS COMPARED WITH TI’S TL16C752B

DATA COMMUNICATIONS APPLICATION NOTE
DAN130
1.3.2 Firmware Differences Between the XR16L2750 and TL16C752B
The internal registers in the XR16L2750 and TL16C752B are similar but with some exceptions:
TABLE 3: XR16L2750 AND TL16C752B REGISTER SET DIFFERENCES
A2:A0 R/W
XR16L2750
TL16C752B
LCR Bit-7 = 0
100 R/W Modem Control Register (MCR)
• Bit-6 = Infrared Mode Enable
Modem Control Register (MCR)
• Bit-6 = TCR and TLR Register Enable
• Bit-2 = Reserved (RI# during Internal Loop- • Bit-2 = FIFO Rdy Register Enable
back)
LCR Bit-7 = 0, MCR Bit-6 = 1 (EFR Bit-4 = 1), MCR Bit-4 = 0, MCR Bit-2 = 0
110 R/W
N/A
Transmission Control Register (TCR)
• RX FIFO Trigger Level Halt and Resume Trans-
mission Levels (4-60 in multiples of 4)
111 R/W
N/A
Trigger Level Register (TLR)
• TX and RX Trigger Levels (4-60 in multiples of 4)
LCR Bit-7 = 0, MCR Bit-6 = 0 (EFR Bit-4 = 1), MCR Bit-4 = 0, MCR Bit-2 = 1
111
R
N/A
FIFO Ready Register (FIFO Rdy)
• Status Bits - TX FIFO level below TX Trigger Level
for channels A and B
• Status Bits - RX FIFO level above RX Trigger
Level for channels A and B
LCR Bit-7 = 0, FCTR Bit-6 = 1
111
W Enhanced Mode Select Register (EMSR)
N/A
• 8X Sampling, LSR Interrupt Immediate, Auto
RTS Hysteresis Select (MSB), RS485 Output
Inversion, FLVL select - TX or RX FIFO
111
R FIFO Level Register (FLVL)
N/A
• Current Level of the TX or RX FIFO
LCR Bit-7 = 0, DLL = 0x00, DLM = 0x00
000
R Device Revision (DREV)
N/A
001
R Device ID (DVID)
N/A
LCR = 0xBF
000
R FIFO Data Count Register (FC)
N/A
000
W Trigger Level Register (TRG)
N/A
• Programmable Trigger Levels 1-64 for TX and
RX FIFO
001 R/W Feature Control Register (FCTR)
N/A
• RX/TX Programmable Trigger Level Select,
Scratchpad Swap, Trigger Table Select, Auto
RS485 Enable, RX Infrared Input Inversion,
Auto RTS Hysteresis Select (LSB)
R = Read-Only, W = Write-Only, R/W = Read/Write
4