DAN-130 Datasheet, PDF (2/11 Pages) Exar Corporation – EXAR’S DUARTS COMPARED WITH TI’S TL16C752B

DATA COMMUNICATIONS APPLICATION NOTE
DAN130
1.2 BUS TIMING DIFFERENCES
• The TL16C752B requires that the -CS pin is asserted first before the -IOR or -IOW pin and the -IOR or -IOW
pin must be de-asserted before the -CS pin is de-asserted. During a read, the Exar DUARTs can have either
the -CS or the -IOR signal asserted first and have either signal be de-asserted first. The signals are wire-
ORed in the Exar DUARTs, therefore the second signal asserted will initiate the read cycle and the first sig-
nal de-asserted terminates the read cycle. The same is true during a write for -CS and -IOW. The flexibility
of the Exar DUARTs timing can be important in DSP, ARM, and MIPS designs.
1.3 FIRMWARE DIFFERENCES
1.3.1 Firmware Differences Between the ST16C2550 and TL16C752B
The internal registers in the ST16C2550 and TL16C752B are similar but with some exceptions:
TABLE 1: ST16C2550 AND TL16C752B REGISTER SET DIFFERENCES
A2:A0 R/W
ST16C2550
TL16C752B
LCR Bit-7 = 0
100 R/W
Modem Control Register (MCR)
• Bit-6 = Not Used
Modem Control Register (MCR)
• Bit-6 = TCR and TLR Register Enable
• Bit-2 = Reserved (OP1# during Internal Loop- • Bit-2 = FIFO Rdy Register Enable
back)
LCR Bit-7 = 0, MCR Bit-6 = 1 (EFR Bit-4 = 1), MCR Bit-4 = 0, MCR Bit-2 = 0
110 R/W
N/A
Transmission Control Register (TCR)
• RX FIFO Trigger Level Halt and Resume Trans-
mission Levels (4-60 in multiples of 4)
111 R/W
N/A
Trigger Level Register (TLR)
• TX and RX Trigger Levels (4-60 in multiples of 4)
LCR Bit-7 = 0, MCR Bit-6 = 0 (EFR Bit-4 = 1), MCR Bit-4 = 0, MCR Bit-2 = 1
111
R
N/A
FIFO Ready Register (FIFO Rdy)
• Status Bits - TX FIFO level below TX Trigger Level
for channels A and B
• Status Bits - RX FIFO level above RX Trigger
Level for channels A and B
R = Read-Only, W = Write-Only, R/W = Read/Write
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