XR16M2651 Datasheet, PDF (39/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE

XR16M2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore
eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWERSAVE FEATURE” ON
PAGE 21.
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA = -40^o to +85^oC, Vcc=1.62 - 3.63V, 70 pF load where applicable
SYMBOL
PARAMETER
LIMITS
1.8V ± 10%
MIN
MAX
LIMITS
2.5V ± 10%
MIN
MAX
LIMITS
3.3V ± 10%
MIN
MAX
UNIT
XTAL1 UART Crystal Oscillator
24
24
24 MHz
ECLK External Clock
32
50
64 MHz
T_ECLK External Clock Time Period
15
10
7
ns
T_AS Address Setup Time (16 mode)
0
0
0
ns
T_AH Address Hold Time (16 mode)
0
0
0
ns
T_CS Chip Select Width (16 mode)
65
40
35
ns
T_RD IOR# Strobe Width (16 mode)
65
40
35
ns
T_DY Read Cycle Delay (16 mode)
65
40
35
ns
T_RDV Data Access Time (16 mode)
60
35
30 ns
T_DD Data Disable Time (16 mode)
25
25
25 ns
T_WR IOW# Strobe Width (16 mode)
65
40
35
ns
T_DY Write Cycle Delay (16 mode)
65
40
35
ns
T_DS Data Setup Time (16 mode)
20
10
10
ns
T_DH Data Hold Time (16 mode)
3
3
3
ns
T_ADS Address Setup (68 Mode)
0
0
0
ns
T_ADH Address Hold (68 Mode)
0
0
0
ns
T_RWS R/W# Setup to CS# (68 Mode)
0
0
0
ns
T_RDA Read Data Access (68 mode)
60
35
30 ns
T_RDH Read Data Disable (68 mode)
25
25
25 ns
T_WDS Write Data Setup (68 mode)
20
10
10
ns
T_WDH Write Data Hold (68 Mode)
3
3
3
ns
T_RWH CS# De-asserted to R/W# De-asserted (68 Mode)
5
5
5
ns
T_CSL CS# Width (68 Mode)
65
40
35
ns
T_CSD CS# Cycle Delay (68 Mode)
65
40
35
ns
T_WDO Delay From IOW# To Output
50
50
50 ns
T_MOD Delay To Set Interrupt From MODEM Input
50
50
50 ns
T_RSI Delay To Reset Interrupt From IOR#
50
50
50 ns
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