XR16M2651 Datasheet, PDF (1/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE

XR16M2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
MAY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XR16M2651¹ (M2651) is a high performance
dual universal asynchronous receiver and transmitter
(UART) with 32 byte TX and RX FIFOs. The device
operates from 1.62 to 3.63 volts and is pin-to-pin and
software compatible to the XR16V2551 and
XR16L2551. The device includes 2 additional
capabilities over the XR16M2650: Intel and Motorola
data bus selection and a “PowerSave” mode to
minimize the sleep current. It supports Exar’s
enhanced features of selectable FIFO trigger level,
automatic hardware (RTS/CTS) and software flow
control, and a complete modem interface. An internal
loopback capability allows system diagnostics.
Independent programmable fractional baud rate
generators are provided in each channel to select
data rates up to 16 Mbps at 3.3 Volt with 4X sampling
clock. The M2651 is available in 48-pin TQFP and 32-
pin QFN packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 1.62 to 3.63 Volt Operation
• Pin-to-pin and software compatible to Exar’s
XR16L2551, XR16V2551 and XR16M2551
• Two independent UART channels
■ Register set is 16550 compatible
■ Data rate of up to 16 Mbps at 3.3 V
■ Data rate of up to 12.5 Mbps at 2.5 V
■ Data rate of up to 8 Mbps at 1.8V
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 32 bytes
■ Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode with wake-up interrupt
■ Full modem interface
• PowerSave Feature reduces sleep current to 15 µA
• Device Identification and Revision
• Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
• 48-TQFP and 32-QFN packages
FIGURE 1. XR16M2651 BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR# (VCC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset (Reset#)
16/68#
CLKSEL
Intel or
Motorola
Data Bus
Interface
UART Channel A
UART
Regs
BRG
32 Byte TX FIFO
TX & RX
IR
ENDEC
32 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
1.62 to 3.63V VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
CTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com