XR22801 Datasheet, PDF (38/42 Pages) Exar Corporation – Hi-Speed USB to 10/100 Ethernet Bridge

XR22801
EDGE_INTR_MASK (0x3C9) - Read/Write
Bit
15:8
7:0
Default
Description
0x00
0x00
Reserved
These bits are reserved and should be written as ‘0’.
E[7:0]
Writing a ’1’ in this register enables an input pin for the corresponding bit position EDGE IO pin(s) configured as
an input to generate an interrupt if either EDGE_INTR_POS_EDGE and / or EDGE _INTR_NEG_EDGE regis-
ters has also been enabled. An EDGE pin configured as an output has no effect.
0: IO pin will not generate an interrupt
1: IO pin assigned to EDGE function and configured as an input will generate an interrupt
EDGE_INTR_POS_EDGE (0x3CA) - Read/Write
Bit
15:8
7:0
Default
Description
0xFF
0xFF
Reserved
These bits are reserved and should be written as ‘1’.
E[7:0]
Writing a ’1’ in this register enables an interrupt to be generated on the rising edge of the corresponding bit posi-
tion EDGE IO pin(s) configured as an input if the EDGE_INTR_MASK register is enabled for that pin. If the
EDGE_INTR_NEG_EDGE register is also enabled, interrupts will be generated on both edges. Writing to an
EDGE pin configured as an output has no effect.
0: IO pin will not generate an interrupt on rising edge
1: IO pin assigned to EDGE function and configured as an input will generate an interrupt on rising edge if cor-
responding EDGE_INTR_MASK bit is set
EDGE_INTR_NEG_EDGE (0x3CB) - Read/Write
Bit
15:8
7:0
Default
Description
0xFF
0xFF
Reserved
These bits are reserved and should be written as ‘1’.
E[7:0]
Writing a ’1’ in this register enables an interrupt to be generated on the falling edge of the corresponding bit
position EDGE IO pin(s) configured as an input if the EDGE_INTR_MASK register is enabled for that pin. If the
EDGE_INTR_POS_EDGE register is also enabled, interrupts will be generated on both edges. Writing to an
EDGE pin configured as an output has no effect.
0: IO pin will not generate an interrupt on falling edge
1: IO pin assigned to EDGE function and configured as an input will generate an interrupt on falling edge if cor-
responding EDGE_INTR_MASK bit is set
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