XR22801 Datasheet, PDF (12/42 Pages) Exar Corporation – Hi-Speed USB to 10/100 Ethernet Bridge

XR22801
UART receiver - Wide mode with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-
ond byte consists of the error bits and break status. Wide mode receive data format is shown in Figure 2. Use the
RX_WIDE_MODE register to enable receive wide mode. Use the RX_WIDE_MODE register to enable receive wide mode.
UART receiver - Wide mode with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of the received
data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received / checked. The remainder of
the 2nd byte consists of the framing and overrun error bits and break status.
1st byte
2nd byte
1st byte
2nd byte
7 or 8 bit mode
76543210
x x x x OF B P
9 bit mode
76543210
x x x x OF B 8
7 = ‘0’ in 7 bit mode
P = Parity Error (= ‘0’ if not enabled)
B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
Figure 2: UART Receive Wide Mode Data Format with 7, 8 or 9-bit data
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags are historical
flags indicating that an error has occurred since the previous request. Therefore, no conclusion can be drawn as to which
specific byte(s) may have contained an actual error in this manner.
RX FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize bytes (512 bytes in hi-speed mode and 64 bytes in full-
speed mode) to improve throughput and to minimize host processing. When there are 512 / 64 bytes of data in the RX FIFO,
the XR22801 will acknowledge a bulk-in request from the host and transfer the data packet. If there is less than 512 bytes in
the RX FIFO, the XR22801 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if
there is less than 512 bytes in the RX FIFO and no data has been received for more than 3 character times, the XR22801
will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this increases latency unacceptably. The XR22801 has a low latency
register bit that will cause the XR22801 to immediately transfer any received data in the RX FIFO to the USB host, i.e. it will
not wait for 3 character times. The custom driver may automatically set the RX_CONTROL register to force the XR22801 to
be in the low latency mode, or the user may manually set this bit. With the CDC-ACM driver, the low latency mode is auto-
matically set whenever the baud rate is set to a value of less than 46921 bps using the CDC_ACM_IF_SET_LINE_COD-
ING command.
© 2015 Exar Corporation
12 / 42
exar.com/XR22801
Rev 1B