XR16V2552_07 Datasheet, PDF (33/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

XR16V2552
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
4.11 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 13 below and SEE”PROGRAMMABLE BAUD
RATE GENERATOR WITH FRACTIONAL DIVISOR” ON PAGE 10.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 13 below.
TABLE 13: SAMPLING RATE SELECT
DLD[5]
DLD[4]
SAMPLING RATE
0
0
16X
0
1
8X
1
X
4X
DLD[7:6]: Reserved
4.12 Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
• Logic 0 = No concurrent write (default).
• Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
BIT-2
0
0
1
1
BIT-1
0
1
0
1
MF# FUNCTION
OP2# (default)
BAUDOUT#
RXRDY#
Reserved
AFR[7:3]: Reserved
All are initialized to logic 0.
4.13 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x02 for XR16V2552). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
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