XR16V2552_07 Datasheet, PDF (3/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

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PIN DESCRIPTIONS
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
Pin Description
NAME
32-QFN
PIN #
DATA BUS INTERFACE
A2
7
A1
6
A0
3
D7
2
D6
1
D5
32
D4
31
D3
30
D2
29
D1
28
D0
27
IOR#
14
44-PLCC
PIN #
15
14
10
9
8
7
6
5
4
3
2
24
IOW#
11
20
CS#
10
18
CHSEL
8
16
INTA
21
34
INTB
9
17
TXRDYA#
-
1
TXRDYB#
-
32
MODEM OR SERIAL I/O INTERFACE
TXA
23
38
TYPE
DESCRIPTION
I Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
I/O Data bus lines [7:0] (bidirectional).
I Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
I Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
I UART chip select (active low). This function selects channel A or B in
accordance with the logical state of the CHSEL pin. This allows data to
be transferred between the user CPU and the V2552.
I Channel Select - UART channel A or B is selected by the logical state
of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects
the UART channel B while a logic 1 selects UART channel A. Normally,
CHSEL could just be an address line from the user CPU such as A4.
Bit-0 of the Alternate Function Register (AFR) can temporarily override
CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially
useful during the initialization routine.
O UART channel A Interrupt output (active high). A HIGH indicates chan-
nel A is requesting for service. For more details, see Figures 17- 22.
O UART channel B Interrupt output (active high). A HIGH indicates chan-
nel B is requesting for service. For more details, see Figures 17- 22.
O _{UART channel A Transmitter Ready (active low). The output provides}
the TX FIFO/THR status for transmit channel A. See Table 2.
O UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See Table 2.
O _{UART channel A Transmit Data or infrared encoder data. Standard}
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
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