XR21B1424 Datasheet, PDF (31/61 Pages) Exar Corporation – Enhanced 4-Ch Full-Speed USB UART

XR21B1424
Table 7: Data Field of Standard Interrupt Packet
Bit
D15:7
D6
Field
bOverRun
D5
bParity
D4
bFraming
D3
bRingSignal
D2
bBreak
D1
bTxCarrier
D0
bRxCarrier
Description
Reserved (future use)
Received data has been discarded due to overrun in
the device.
A parity error has occurred.
A framing error has occurred.
State of ring signal detection of the device.
State of break detection mechanism of the device.
State of transmission carrier. This signal corresponds
to V.24 signal 106 and RS-232 signal DSR.
State of receiver carrier detection mechanism of
device. This signal corresponds to V.24 signal 109
and RS-232 signal DCD.
If the Exar vendor specific packet mapping is enabled then the interrupt packet format is as shown in Table 8.
Table 8: Customized Interrupt Packet Format
Offset
Field
0
GPIO_STATE
2
GPIO_INT
4
Data
Size
(Bytes)
2
2
1
Value
Description
Byte 0: GPIO_STATE[7:0]
Byte 1: GPIO_STATE[9:8]
Byte 2: GPIO_INT[7:0]
Byte 3: GPIO_INT[9:8]
D15:4 = Reserved (0)
D3 = Overrun Error
D2 = Parity Error
D1 = Frame Error
D0 = Break Status
PIN_OPEN_DRAIN (0x013) - Read/Write
This register controls all pins configured as outputs irrespective of if they are configured as GPIO or alternate functions.
Bit
15:12
11
10
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
UART TX
0: TX Pin is push-pull output
1: TX Pin pin is open drain output
0
Reserved
These bits are reserved and should be written as ‘0’.
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